LDO Headroom and Its Effects on Output Noise and PSRR
The latest multigigahertz analog circuits, built on deep submicron processes, require ever-lower power supply voltages, in some cases less than 1 V. These high-frequency circuits often require a considerable amount of supply current, so thermal management can become difficult. A design goal is to reduce power dissipation to that which is absolutely necessary for circuit performance.
Switch-mode dc-to-dc converters make the most efficient power supplies, with some devices exceeding 95% efficiency, but this high efficiency comes at the cost of increased power- supply noise, often over a wide bandwidth. Low-dropout linear regulators (LDOs) are frequently used to clean up noisy supply rails, but they also present trade-offs, dissipating power and increasing the system’s thermal load. To minimize these problems, LDOs can be operated with a smaller difference (headroom voltage) between input and output voltages. This article discusses the impact of low-headroom voltage operation on power-supply rejection and total output noise.
LDO Power-Supply Rejection vs. Headroom
LDO power-supply rejection ratio (PSRR) is strongly dependent on headroom voltage—the difference between the input and output voltages. For a fixed headroom voltage, PSRR decreases as the load current increases; this is especially true with large load currents and small headroom voltages. Figure 1 shows the PSRR for the ADM7160 ultralow-noise, 2.5-V linear regulator with 200-mA load current and 200-mV, 300-mV, 500-mV and 1-V headroom voltages. As the headroom voltage decreases, the PSRR decreases, and the difference can be dramatic. For example, at 100 kHz, changing the headroom voltage from 1 V to 500 mV results in a 5-dB decrease in PSRR. However, a smaller change in headroom voltage, from 500 mV to 300 mV, causes the PSRR to drop more than 18 dB.
Figure 2 shows a block diagram of the LDO. As the load current increases, the gain of the PMOS pass element decreases as it leaves saturation and enters the triode region. This causes the overall loop gain to decrease, resulting in lower PSRR. The smaller the headroom voltage, the more dramatic the reduction in gain. As the headroom voltage continues to decrease, it reaches a point at which the gain of the control loop drops to 1, and the PSRR falls to 0 dB.
Another factor that reduces the loop gain is the resistance of the pass element, which includes the FET’s on resistance, the on-chip interconnect resistance, and the wire bonds. An estimate of this resistance can be derived from the dropout voltage. For example, the ADM7160 in the WLCSP package has a maximum dropout voltage of 200 mV at 200 mA. Using Ohm’s law, the resistance of the pass element is about 1 Ω. The pass element can be approximated as a fixed resistor plus a variable resistance.
Voltage drops due to the load current flowing through this resistance subtract from the drain-to-source operating voltage of the FET. For example, with a 1-Ω FET, a load current of 200 mA reduces the drain-to-source voltage by 200 mV. When estimating the PSRR of LDOs operating with 500-mV or 1-V headroom, the voltage drop across the pass element must be taken into account, as the pass FET is effectively operating with only 300 mV or 800 mV.
Effect of Tolerances on LDO Headroom
Customers often ask applications engineers to help them select an LDO to generate low-noise voltage X from input voltage Y at load current Z, but one factor frequently ignored when setting these parameters is the tolerance of the input and output voltages. As headroom voltage falls to lower and lower values, the tolerance of the input and output voltages can dramatically affect the operating conditions. The worst-case tolerance of the input and output voltages always results in a lower headroom voltage. For example, the worst-case output voltage can be 1.5% high and the input voltage can be 3% low. When a 3.3-V regulator is powered by a 3.8-V source, the worst-case headroom voltage is 336.5 mV, far lower than the expected 500 mV. With the worst-case load current of 200 mA, the drain-to-source voltage of the pass FET is only 136.5 mV. The PSRR of the ADM7160 in this case can be expected to fall far short of the published 55 dB at 10 mA.
PSRR of an LDO Operating in Dropout
Customers frequently ask applications engineers about an LDO’s PSRR in dropout. Initially this may seem like a reasonable question, but a glance at the simplified block diagram will show it to be meaningless. When the LDO is in dropout, the variable resistance portion of the pass FET is zero, and the output voltage is equal to the input voltage minus the voltage drop due to the load current through the RDSON of the pass FET. The LDO is not regulating and has no gain to reject noise on the input; it is simply operating as a resistor. The RDSON of the FET forms an RC filter with the output capacitor, providing a small amount of residual PSRR, but a simple resistor or ferrite bead could perform the same job much more cost effectively.
Maintaining Performance when Operating with Low Headroom
It is imperative to consider the effect of headroom voltage on PSRR when operating at low headroom, as failure to do so will result in a noisier output voltage than expected. PSRR vs. headroom voltage plots, such as that shown in Figure 3, are usually found in the data sheet and can be used to determine the amount of noise rejection possible for a given set of conditions.
However, it’s sometimes easier to see how to apply this information by demonstrating how the LDO’s PSRR effectively filters out the noise of the source voltage. The following plots show the impact on the total output noise of an LDO when operating at different headroom voltages.
Figure 4 shows the output noise of a 2.5-V ADM7160 with 500-mV headroom and 100-mA load compared to the baseline noise of an E3631A bench supply, which specifies less than 350-μV-rms noise from 20 Hz to 20 MHz. The many spurs below 1 kHz are harmonics related to rectification of the 60-Hz line frequency. The broad spur above 10 kHz is from the dc-to-dc converter that generates the final output voltage. The spurs above 1 MHz are due to RF sources in the environment unrelated to the power-supply noise. The measured noise of the supply used for these tests is 56 μV rms from 10 Hz to 100 kHz and 104 μV rms including the spurs. The LDO rejects all of the noise on the power supply, and has about 9-μV-rms output noise.
As the headroom voltage drops to 200 mV, the noise spurs above 100 kHz begin to poke though the noise floor as the high-frequency PSRR approaches 0 dB. The noise rises slightly to 10.8 μV rms. As the headroom falls to 150 mV, rectification harmonics start to affect the output noise, which rises to 12 μV rms. A moderate peak appears at about 250 kHz, so sensitive circuitry may be adversely affected even though the increase in total noise is modest. As the headroom voltage drops further, performance becomes compromised, and spurs related to rectification become visible in the noise spectrum. Figure 5 shows the output with 100-mV headroom. The noise has risen to 12.5 μV rms. The harmonics contain very little energy, so the noise with spurs is only slightly higher at 12.7 μV rms.
With 75-mV headroom, the output noise becomes severely compromised, and rectification harmonics appear throughout the spectrum. The rms noise rises to 18 µV rms and the noise plus spurs rises to 27 μV rms. The noise beyond 200 kHz is attenuated because the LDO loop has no gain and acts as a passive RC filter. With 65-mV headroom, the ADM7160 is operating in dropout. As shown in Figure 6, the output voltage noise of the ADM7160 is essentially the same as the input noise. The rms noise is now 53 μV rms and the noise plus spurs is 109 μV rms. The noise beyond 100 kHz is attenuated because the LDO is acting as a passive RC filter.
Ultralow-Noise LDOs with High PSRR
A new class of LDOs such as the ADM7150 ultralow-noise, high-PSRR regulator essentially cascade two LDOs, so the resulting PSRR is approximately the sum of that of the individual stages. These LDOs require somewhat higher headroom voltages but are able to achieve PSRRs exceeding 60 dB at 1 MHz and well over 100 dB at lower frequencies.
Figure 7 shows the noise spectral density of a 5-V ADM7150 with 500-mA load current and 800-mV headroom. The output noise is 2.2 μV rms from 10 Hz to100 kHz. As the headroom drops to 600 mV, the rectification harmonics start to become apparent, but the effect on the noise is small as the output noise rises to 2.3 μV rms.
With 500-mV headroom, rectification harmonics and a peak at 12 kHz are clearly visible, as shown in Figure 8. The output voltage noise rises to 3.9 μV rms.
With 350-mV headroom, the LDO is in dropout. No longer able to regulate the output voltage, the LDO acts like a resistor, and the output noise has risen to nearly 76 μV rms, as shown in Figure 9. The input noise is only attenuated by the pole formed by the RDSON of the FET and the capacitance at the output.
Modern LDOs are increasingly being used to clean up dirty power supply rails, which are often implemented with switching regulators that generate noise over a broad spectrum. The switching regulators create these voltage rails at high efficiency, but the dissipative LDOs reduce both noise and efficiency. Therefore, LDOs should be operated with as little headroom voltage as possible.
As shown, their PSRR is a function of both load current and headroom voltage, decreasing as the load current increases or the headroom voltage decreases due to the reduced loop gain as the operating point of the pass transistor moves from the saturation region to the triode region.
Considering the input source noise characteristics, PSRR, and worst-case tolerances allows designers to optimize both the power dissipation and output noise to achieve an efficient, low-noise power supply for sensitive analog circuits.
When operating at very low headroom voltages, the worst-case tolerance of the input and output voltages can affect the PSRR. Designing for worst-case tolerances will ensure a robust design; failure to do so will yield a power solution with lower PSRR resulting in higher than expected total noise.
Morita, Glenn. “Noise-Reduction Network for Adjustable- Output Low-Dropout Regulators.” Analog Dialogue, Volume 48, Number 1, 2014.
Morita, Glenn. “Low-Dropout Regulators—Why the Choice of Bypass Capacitor Matters.” Analog Dialogue, Volume 45, Number 1, 2011.
Morita, Glenn. AN-1120 Application Note. Noise Sources in Low-Dropout (LDO) Regulators. Analog Devices, Inc., 2011.