摘要

This article provides an inverting buck-boost solution for fast-transient, noise-sensitive negative voltage rail applications. The solution utilizes a monolithic buck converter that incorporates the Silent Switcher^® 3 (SS3) technology in an inverting buck-boost (IBB) topology. The solution is thoroughly tested to meet several key requirements, including minimum load transient peak-to-peak voltage, minimum low frequency noise, minimum bulk output capacitance and inductor size, and high efficiency. The performance is further enhanced by fully leveraging the speed capabilities of the SS3 technology. The article provides detailed design tips and considerations of the solutions to assist engineers with future designs.

Introduction

Negative voltage supplies are found in various applications, such as in digital-to-analog converter (DAC) and analog-to-digital converter (ADC) drivers in signal chains, power amplifiers in displays and RF, imaging systems, optical diodes, and biasing for automatic test equipment (ATE) to achieve a true 0 V output. These applications are often sensitive to power supply noise, encompassing not only the fundamental switching frequency and higher frequencies, but also low frequency noise ranging from the switching frequency down to 0.1 Hz. To mitigate this low frequency noise, power supply designers often resort to using a postfilter low dropout (LDO) regulator. However, this approach increases solution size and reduces efficiency. The Silent Switcher^® 3 family of ultralow noise monolithic buck converters provides an excellent solution for applications that demand minimal low frequency output noise without the need for an LDO regulator. The SS3’s high switching speed, control loop bandwidth, and impressive low frequency noise performance are not limited to buck applications alone. By reconfiguring the simple half-bridge topology, the SS3 can be employed as an inverting buck-boost (IBB) converter to generate negative output voltages. This slight modification to the architecture enables the SS3 to operate in applications where a negative voltage rail requires low frequency noise performance. Traditionally, such a solution would involve two stages: an IBB or CÜK converter as the first stage to generate a negative voltage, and a negative voltage LDO regulator as a postfilter stage to satisfy the low frequency noise requirements. However, in applications where solution size (height and area) is a top priority, this approach is undesirable. In addition to eliminating the need for an LDO regulator to reduce solution size, the high switching frequency and control loop bandwidth of the SS3 can be leveraged to reduce the size of the inductor and bulk output capacitance.

This article serves as a comprehensive design guide for utilizing the LT8624S, a member of the SS3 family, as an IBB in a negative voltage application. The design guide is presented in the form of a customer request, outlining a set of challenging solution specifications. A comparison is made with the closest competitor in terms of low frequency noise performance. The design process also addresses the specific challenges associated with an IBB, such as determining the appropriate inductor size for load current, and provides a simple tip for increasing the control loop bandwidth by shifting the IBB’s right-half-plane zero (RHPZ) to a higher frequency.

Negative Voltage Application

In the following application, a power amp requires a negative supply voltage of -5 V. The rail will be powered by a 5 V source and must adhere to a low profile height limit of 2 mm while maintaining a compact form factor. Table 1 provides a full detailed list of specifications. Using the LT8624S as an IBB is an ideal solution for this application due to its speed and low frequency noise performance, enabling a compact solution size while maintaining good efficiency. The schematic is shown in Figure 1.

It is important to note that when using a monolithic buck regulator as an IBB, the IC is referenced to –V_OUT instead of GND. This distinction is crucial when determining the maximum output voltage. The output voltage can be calculated using Equation 1, where V_{IC Max rating} represents the maximum voltage rating for the IC when used as a buck converter. For the LT8624S this rating is 18 V. Additionally, since the IC is referenced to the output voltage, any external control signals required, such as for enabling the IC or synchronizing to an external clock, the (EN/UVLO and SYNC/MODE pins) will need a level shifter circuit to adjust the signal’s reference to the IC. An example of a level shifter is shown in Figure 1.

Designing the Inductor and Determining the Switching Frequency

When designing a compact IBB solution, minimizing the inductor size is crucial. The first task in selecting the appropriate inductor is to identify a family of inductors that will fit optimally within the customer’s specified size requirements. This can be achieved by maximizing the height limitation of 2 mm and minimizing the area of the inductor. It is important to consider that a physically larger inductor will typically provide greater current capability and power efficiency.

To begin the search, high performance XGL series of shielded inductors from Coilcraft can be considered. Despite the 2 mm height spec, the selection of inductors is extensive, necessitating further filtering. This can be accomplished by calculating the average and peak inductor current at full load using equations 2 and 3. Where IL represents the average inductor current, I_PEAK denotes the peak inductor current, 0.4 accounts for the 40% AC inductor ripple current, and n represents the converter efficiency.

It is important to note that, unlike a buck converter, an IBB’s average inductor current is the sum of both the input and output currents. This characteristic adds complexity to the design of the inductor because the input current can vary. Consequently, the inductor’s size will likely be larger than a buck converter. Assuming a 90% efficiency with a 40% AC ripple current at full load, the calculated average inductor current based on the customer’s full load specs is about 2.1 A, with a peak current of 2.52 A. With these calculated current values in mind, an appropriate inductor can be selected. The selected inductor’s I_RMS rating should be greater than the average inductor current of 2.1 A, and ideally, the I_SAT (current at which inductance drops by 10%) should be greater than the peak inductor current of 2.52 A. Considering these factors, including the requirement for minimum area, the XGL4020 family of inductors was chosen. Within this family, the 2.2 µH and 1.5 µH inductors were selected as potential options. To determine the optimal inductor, a series of full load efficiency tests were conducted by sweeping across a range of different switching frequencies. The goal was to achieve at least 90% efficiency with the highest frequency.

The results indicated that the optimal combination was a 1.5 µH inductor operating at a frequency of 2.2 MHz. At full load, the efficiency reached 90.2%, meeting the customer’s requirement. Figure 2 shows the efficiency curve with the 1.5 µH inductor at 2.2 MHz.

Designing the Bulk Output Capacitance

Once the inductor and switching frequency have been determined, the next task is to design the bulk output capacitance for the IBB. Similar to the inductor selection, the output capacitors must adhere to the 2 mm height limit and occupy minimal area to satisfy the customer’s application requirements. In addition, there must be sufficient output capacitance to perform a half load to full load transient with a peak-to-peak output voltage of 40 mV. The capacitors must also be derated at 5 V. To identify the optimal capacitor, the supplier Murata was used due to their well-documented and extensive range of capacitors. By comparing the derated output capacitances of various parts, 22 µF 0805 capacitors were chosen as they offered the highest capacitance within the size requirement.

With the capacitor selected, the total amount of bulk output capacitance needs to be determined. This can be achieved by conducting a series of load transient bench tests based on the customer’s specs. The approach is to initially use a more than reasonable amount of capacitance, such as ten 22 µF capacitors, to satisfy the peak-to-peak output voltage requirement and ensure stability. Subsequently, capacitors are gradually removed until the output voltage peak-to-peak is just below 40 mV, while ensuring that the compensation remains stable and optimal.

In addition, a full load bode plot test should be performed to verify that the control loop exhibits a phase margin of at least 45° and a gain margin of 8 dB.

Through this process, the bulk output capacitance was optimized to seven 22 µF capacitors, resulting in a V_OUT with a peak-to-peak voltage of 36 mV during a 0.5 A to 1 A to 0.5 A load transient, with a 0.5 A/µs slew rate. This satisfies the customer’s requirement of a 40 mV p-p output voltage. The load transient results are shown in Figure 3.

The bode plot at 1 A shows a bandwidth of 103 kHz, a phase margin of 53°, and a gain margin of 8.2 dB, all of which fall within the expected range. The bode plot is shown in Figure 4.

Low Frequency Noise Measurement and Competitor Comparison

It is important to consider the customer’s application, which is sensitive to noise in the frequency range of 10 Hz to 1 MHz. The required integrated noise within this range should be below 25 µV rms. This noise range can be easily measured using a spectrum analyzer and amplifier. Testing the solution designed as described above, the integrated noise from 10 Hz to 1 MHz was measured to be 22 µV rms, which is below the customer’s minimum requirement. For comparison, the closest competitor to the SS3, using the same test conditions, including the inductor, output capacitors, and switching frequency, has an integrated noise of 90 µV rms. The noise test results are shown in Figure 5.

Increasing the Control Loop Bandwidth of an SS3 IBB

Upon reviewing the results, the customer provided updated specifications for their application. They discovered that their power amp requires a minimum integrated noise of 20 µV rms within the 10 Hz to 1 MHz range, as well as a V_OUT load transient tolerance of less than 35 mV p-p. Unfortunately, the current design does not meet these new requirements, so improvements must be made to enhance performance. Fortunately, the SS3 offers high speed control loop capabilities, enabling faster load transients and lower noise without the need for additional output capacitance.

To fully leverage the fast control loop of the SS3, the IBB’s RHPZ needs to be relocated. The RHPZ causes a gain boost and phase delay in the control loop, limiting the converter’s bandwidth, thus reducing the performance of the SS3. Based on the current design with the 1.5 µH inductor, the RHPZ is located at approximately 265 kHz, causing the converter to experience phase loss around 27 kHz. The RHPZ frequency location can be determined using Equation 4, where L represents the inductance of the inductor.

Equation 4. Used to calculate the frequency location of the RHPZ.

By observing the equation, it is evident that the RHPZ location is inversely proportional to the inductance of the inductor. This implies that the RHPZ can be shifted to a higher frequency by using an inductor with lower inductance. By moving the RHPZ to a higher frequency, the control loop bandwidth can be increased. However, to maintain the same inductor ripple current, the switching frequency needs to be higher. The next available inductor size in the XGL4020 family is 1 µH, so the switching frequency should be raised to 3.3 MHz. This can be easily achieved with the SS3’s 6 MHz switching capability. The new RHPZ location would be approximately 398 kHz, which should be sufficient to push the control loop bandwidth to a higher frequency. The schematic for the revised design is shown in Figure 6.

Control Loop Comparisons

To validate the improvement in bandwidth, a bode plot test was conducted at 5 V_IN, –5 V_OUT, and a 1 A load. The test results, along with a comparison to the previous design, are shown in Figure 7. The results indicate an increase in bandwidth from 103 kHz to 123 kHz, a phase margin of 54°, and a gain margin of 9.8 dB. It is important to note that the control loop was recompensated to achieve a similar phase margin as the 1.5 µH design.

With the new design demonstrating approximately a 20% enhancement in control loop speed, the same 0.5 A to 1 A to 0.5 A load transient, as in the initial design, was performed. The measurement showed a peak-to-peak output voltage of 30 mV. The results are compared to the 1.5 µH design in Table 2.

Low Frequency Noise Comparisons

Next, the low frequency noise was tested to determine if it met the new 10 Hz to 1 MHz integrated requirement. The results indicate that the integrated noise measures 18.9 µV rms, which falls within the new 20 µV rms spec. This outcome is compared to the 1.5 µH design, and the noise curve is shown in Figure 8.

Efficiency Comparisons

It is necessary to re-evaluate the full load efficiency, considering that the converter’s switching frequency has increased by 50% compared to the initial design. The efficiency test results are shown in Figure 9. The measurement indicates a full load efficiency of 89.5%. While this falls slightly below the 90% requirement, the customer was satisfied with the result, as efficiency was of lower priority in their design.

Conclusion

The SS3 family of monolithic buck regulators can be seamlessly transformed into an inverting buck-boost regulator, to create a negative voltage rail. These regulators offer unparalleled low frequency noise performance for a switching regulator, along with high control loop and switching speeds. As a result, they serve as ideal solutions for negative voltage applications that require a fast transient and are noise sensitive.