ad14160l
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ad14160l

480-MFLOP, Quad DSP, 3.3v, CBGA Package

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产品详情
特性
  • ADSP-21060 Core Processor(...x4)
  • 480 MFLOPS Peak, 320 MFLOPS Sustained
  • 25 ns Instruction Rate, Single-Cycle Instruction Execution-Each of Four Processors
  • 16 Mbit Shared SRAM (Internal to SHARCs)
  • 4 Gigawords Addressable Off-Module Memory
  • Sixteen 40 Mbyte/s Link Ports (Four per SHARC)
  • Eight 40 Mbit/s Independent Serial Ports (Two from Each SHARC)
  • 5 V and 3.3 V Operation
  • 32-Bit Single Precision and 40-Bit Extended Precision IEEE Floating Point Data Formats,
    or 32-Bit FixedPoint data Format
  • IEEE JTAG Standard 1149.1 Test Access Port and On-Chip Emulation
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The AD14160 Quad-SHARC Ceramic Ball Grid Array (CBGA) puts the power of the first generation AD14060 (CQFP) DSP multiprocessor into a very high density ball grid array package; now with additional link and serial I/O pinned out, beyond that from the CQFP package. The core of the multiprocessor is the ADSP-21060 DSP Microcomputer. The AD14X60 modules have the highest performance-density and lowest cost-performance ratios of any in their class. They are ideal for applications requiring higher levels of performance and/or functionality per unit area.

The modules embed several hundred feet of highly-optimized signal interconnect into the package, eliminating complexity and design time from your PCB design. The result is unmatchable performance in a robust little package. Also, board complexity, board layers, and even entire boards can now be eliminated from your system.

The AD14160 takes advantage of the built-in multiprocessing features of the ADSP-21060, to achieve 480 peak MFLOPS with a single chip type, in a single package. The on-chip SRAM of the DSPs provides 16 Mbits of on-module shared SRAM. The complete shared bus (48-bit data, 32-address) is also brought off-module for interfacing with expansion memory and/or other peripherals.

The ADSP-21060 link ports are interconnected to provide direct communication among the four SHARCs as well as a high-speed off-module access. Internally, links connect the SHARC in a ring. Externally, each SHARC has a total of 160 Mbytes/sec link port bandwidth.

Multiprocessor performance is enhanced with embedded power and ground planes, matched impedance interconnect, and optimized signal routing lengths and separation. The fully tested and ready-to-insert multiprocessor also significantly reduces board space.

产品技术资料帮助

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ADI公司所提供的资料均视为准确、可靠。但本公司不为用户在应用过程中侵犯任何专利权或第三方权利承担任何责任。技术指标的修改不再另行通知。本公司既没有含蓄的允许,也不允许借用ADI公司的专利或专利权的名义。本文出现的商标和注册商标所有权分别属于相应的公司。

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