AD9993

Obsolete

Integrated Mixed Signal Front End MxFE

Data Sheet (Rev. B) Product Selection Table

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Part Details

Quad 14-bit 250 MSPS ADC:
SFDR = 83 dBc at 87 MHz input
Dual 14-bit 500 MSPS DAC:
SFDR = 75 dBc at 20 MHz output
On Chip PLL Clock Synthesizer
Low Power:
1536 mW, 1 GHz master clock, on-chip synthesizer

500 MHz double data rate (DDR)
LVDS Interfaces for DACs and ADCs
Small 12 mm × 12 mm lead-free BGA package

Documentation

Data Sheet 1

AD9993: Integrated Mixed-Signal Front End (MxFE) Data Sheet (Rev.B) 05/07/2014

This is the most up-to-date revision of the Data Sheet.

Hardware Ecosystem

Parts	Product Life Cycle	Description
Modulators & Demodulators 1
ADRF6720	Obsolete	Wideband (700 MHz to 3 GHz) Quadrature Modulator with Integrated PLL/VCOs and 0.5 V Input Bias
Variable Gain Amplifiers (VGA) 1
ADRF6518	Obsolete	1.1 GHz Variable Gain Amplifiers and Baseband Programmable Filters

Tools & Simulations

IBIS Model 1

AD9993 IBIS Model

Evaluation Kits

AD9993 Evaluation board

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Product Details

The AD9993-EBZ is the evaluation board for the AD9993 which is a mixed-signal front-end (MxFE^®) device that integrates four 14-bit ADCs and two 14-bit DACs.

The MxFE is programmable using registers accessed via a serial peripheral interface (SPI). ADC and DAC data paths include FIFO buffers to absorb phase differences between LVDS lane clocks and the data converter sampling clocks.

The MxFE DACs are part of the Analog Devices, Inc., high speed CMOS DAC core family. These DACs are designed to be used in wide bandwidth communication system transmitter (Tx) signal chains.

The MXFE ADCs are multistage pipelined CMOS ADC cores designed for use in communications receivers.