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ADuC7026 Provides Programmable Voltages for Evaluating Multiple Power Supply Systems
Table 1. AD7656-1 Typical Supply Voltages and Maximum Supply Currents
Table 1 shows the typical voltage and maximum current for each of the ADC’s power supplies. The programmable sequence-controllable voltage waveforms generated by the four DACs on the ADuC7026 are scaled by the ultralow noise-and-distortion AD797 op amps on the AD7656-1 evaluation board to provide the specified supply voltages and currents. The microcontroller’s speed and programmability facilitate control of voltage level, period, pulse width, and ramp time of the power supply voltages.
For example, using external power supplies, the AD797 amplifiers on the AD7656-1 evaluation board, configured for a gain of 5, can generate a voltage range of 0 V to 12.5 V to drive the ADC’s VDD supply rail. The high output drive capability of the AD797 allows up to 50 mA to be provided to each supply rail. Figure 1 shows the connections to the ADC.
Figure 1. AD7656-1 connection diagram.
The ADuC7026 DAC data register can be updated at 7 MHz with a 41.78-MHz core clock, which maximizes the voltage update rate. The following sections describe the development process and provide measurement results obtained using the evaluation boards.
Hardware Development and Setup
Figure 2. Hardware connections and test bench.
Figure 3. AD797 schematic design with gain = 4.
Figure 4 shows the frequency response of the AD797 with gain = 4, from an NI Multisim™ simulation. The 1.0-MHz bandwidth and 73° phase margin provide fast transient response and stable operation.
Figure 4. Frequency response of the AD797 with gain = 4.
AD797 Design Notes
It is not internally compensated for substantial capacitive loads though, so external compensation techniques must be used to optimize this application. Figure 5 shows oscillation on the AD797 output caused by driving capacitive loads.
Figure 5. Oscillations without compensation.
For stable drive with capacitive loads on the power rail, Resistor R4 is placed between the output and the load. This resistor isolates the op amp output and feedback network from the capacitive load and introduces a zero in the transfer function of the feedback network, reducing the phase shift at higher frequencies.1 The feedback capacitor, C2, compensates for the capacitive loading, including C1, at the input of the op amp.
Applying the DACs
Each DAC has three selectable ranges: 0 V to VREF (internal band gap 2.5-V reference), 0 V to DACREF (0 V to AVDD), and
Each of the four DACs is independently configurable through control register DACxCON and data register DACxDAT. Once the DAC is configured through the DACxCON register, data can be written to DACxDAT for the required output voltage level.
The four DAC outputs are easy to control using C or assembly language. This C-code example shows how to choose the internal 2.5-V reference and set the DAC0 output to 2.5 V.
//connect internal 2.5 V reference to VREF pin
REFCON = 0x01;
//enable DAC0 operation
DAC0CON = 0x12;
//update DAC0DAT register with data 0xFFF
DAC0DAT = 0x0FFF0000;
Using assembly language,
DAC0CON is cleared to update DAC0 using core clock (41.78 MHz) for fast update rate;
DAC0CON[1:0] is set to ‘10’ to use 0 V to VREF (2.5 V) output range
‘DAC0DAT = 0x0FFF0000’ can be compiled to assembly code with two instructions:
MOV R0, #0x0FFF0000
STR R0, [R1, #0x0604]
These two instructions take a total of six clock cycles to execute, corresponding to a 7-MHz update rate with a 41.78-MHz core-clock frequency. Thus, the time delay between voltage rails can be as accurate as 144 ns.
Table 2. Power Supplies for AD7656-1
The waveforms from the four DAC outputs, as described in Table 2, were captured using a scope and are shown in Figure 6. The voltage level, period, pulse width, and ramp time of each channel are each programmable and easy to control. The specific parameters are measured and described in the following sections.
Figure 6. Four-channel voltage waveform.
To achieve an accurate voltage level for each power supply, an adjustable resistor can be used for R1 in Figure 3. The voltage level was calibrated by adjusting R1 with an Agilent 34401A digital multimeter.
Rising and falling ramp time are measured to determine the maximum frequency of the voltage waveforms. The ramp time is related to the value of Resistor R4 and the capacitive load, CL. For slower ramp times, larger resistor and capacitor values can be used for R4 and CL. The rising and falling ramp time of AVCC and DVCC were tested with different load capacitors, with the results shown in Table 3. The rising waveform with a 1-µF capacitor is shown in Figure 7. The ramp time is measured between 10% and 90% of 10 V.
Table 3. Ramp Time with Capacitive Load
Figure 7. Rise time with 1-µF capacitive load.
Table 4. Ripple of Each Power Supply
Figure 8. Ripple of 5-V supply on AVCC and DVCC.
Figure 9. 22.32 kHz square waveform.
Figure 10. 13.16 kHz pulse waveform.
The LabVIEW® GUI shown in Figure 11 can be used to generate the power supply waveforms. The voltage level, ramp time, period, and sequence delay time of the four channels are easy to configure. The serial port is used for communication between GUI and the ADuC7026.
Figure 11. Power supply configuration GUI.
With a standard ±15-V dc power module, this portable power supply evaluation systems allows designers to evaluate ADCs, especially for those with larger number of supplies.
1Bendaoud, Soufiane and Giampaolo Marino, Practical Techniques to Avoid Instability Due to Capacitive Loading (Ask the Applications Engineer—32), Analog Dialogue, Volume 38, Number 2 (2004).
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