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New High-Resolution Multiplying DACs Excel at Handling AC Signals
Figure 1. Inverting gain configuration.
A burgeoning market has seen several generations of multiplying DACs, with increased resolution, accuracy, and speed; various digital storage functions; serial-communication options; reduced size and cost; and additional DACs per chip. The latest generation of multiplying DACs offer ideal building blocks for controlling the gain of varying dc or fast ac voltage signals.
The resistance (R-2R) ladder, used in an op-amp feedback circuit, provides a digitally controlled current that is translated to an output voltage by RFB. The amplifier provides this output at low impedance. The reference input has a constant resistance to ground, equal to R. Figure 2 shows the principle. In Figure 2a, one-half of the source current, VREF/R, is steered by switch S1 to either IOUT1, connected to the amplifier's negative input (at virtual ground), or to ground (often called IOUT2). One-half the remaining current is steered similarly by switch S2 ... and so on. If the switches are activated by a digital word, D (S1 is the MSB), the sum of the currents at IOUT1, flowing through RFB (=R), is D × 2n × VREF/R. Important advantages of this configuration include minimization of transients, because the switches are switching between ground and virtual ground, and that RFB is matched on-chip to the ladder resistance, with excellent tracking over temperature.
Figure 2. a) R-2R ladder principle. b) multiplying DAC, VOUT = 0 to −VREF.
The range of values given by the digital word, D, depends on the device used. Here are the ranges of D (first quadrant) for some Analog Devices multiplying DACs in the AD545x/AD554x families:
Figure 3. Increasing the gain of a multiplying DAC.
a differential output is required, two extra op amps are needed. Complete
details can be found in Circuits from the Lab®
Figure 4. Multiplying DAC, VOUT = 0 to VREF. The AD5415, AD5405, AD5546/AD5556, AD5547/AD5557 include uncommitted resistors like those shown here.
Figure 5. Single-ended to differential.
where GBW is the small signal unity-gain bandwidth product of the op amp and CO is the output capacitance of the DAC.
M-DAC Specifications for Signal Conditioning
Figure 6. Multiplying bandwidth.
Analog Total Harmonic Distortion (THD): A mathematical representation of the harmonic content in the multiplied waveform signal. It is approximated by the log ratio of the rms sum of the first four harmonics (V2, V3, V4, and V5) of the DAC output to the fundamental value, V1, shown in Figure 7, and given by the equation:
Figure 7. Harmonic distortion components.
Feedthrough Error: The error due to capacitive feedthrough from
the reference input to the DAC output, when the digital input to the
DAC is all 0s. Ideally with each bit that is dropped, the gain is
reduced by 6 dB, all the way down to the least significant bit, DB0
(Figure 8). However, for the lower bits the capacitive feedthrough
affects the gain at higher frequencies. This can be seen by the flat
lines tailing upwards for the lower bits. For example, at DB2 for
a 14-bit DAC, the ideal gain should be
Figure 8. Multiplying feedthrough error.
the Correct Op Amp
For applications where the reference input is a relatively high speed signal, a wide-bandwidth, high-slew-rate op amp is required to avoid degrading the signal. The gain-bandwidth of an op-amp circuit is limited by the impedance level of the feedback network and the gain configuration. To determine what GBW is required, a useful guideline is to select an op amp with a 3-dB bandwidth that is 10 times the frequency of the reference signal.
The slew-rate specification of the op amp must be considered in order to limit distortion of large high-frequency signals. For the AD54xx and AD55xx families, an op amp with a slew rate of 100 V/µs is generally sufficient.
Table 1 provides a selection of operational amplifiers that are useful for multiplying applications
Table 1. Selection of Sutiable Analog Devices High Speed Op Amps
the Right DAC
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