Download this article in PDF format. (1,478KB) "Rules of the Road" for High-Speed Differential ADC Drivers
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differential ADC drivers have become essential signal conditioning elements
in data-acquisition systems.
A basic fully differential
voltage-feedback ADC driver is shown in Figure 1. Two differences from
a traditional op-amp feedback circuit can be seen. The differential ADC
driver has an additional output terminal (V Instead of a single-ended
output, the differential ADC driver produces a balanced differential output—with
respect to V For the discussions
that follow, some definitions are in order. If the input signal is – V._{IN}The common-mode input
voltage, V, are defined in Equation 1 _{IN, cm}and Equation 2.
This common-mode definition is intuitive when applied to balanced inputs, but it is also valid for single-ended inputs. The output also has a differential mode and a common mode, defined in Equation 3 and Equation 4.
Note the difference
between the actual output common-mode voltage, _{OCM} input terminal, which establishes the output common-mode
level.The analysis of
differential ADC drivers is considerably more complex than that of traditional
op amps. To simplify the algebra, it is expedient to define two feedback
factors, β
In most ADC driving
applications β _{IP}, V_{IN}, V_{OCM}, β_{1}, and β_{2},
is useful to gain insight into how beta mismatch affects performance.
The equation for V, shown in Equation 7, includes
the finite frequency-dependent open-loop voltage gain of the amplifier,
A(s)._{OUT, dm}
When β When β
This is a more familiar-looking
expression; the ideal closed-loop gain becomes simply R The ideal closed-loop gain for a differential ADC driver with matched feedback factors is seen in Equation 9.
Output balance,
an important performance metric for differential ADC drivers, has two
components:
An internal common-mode
feedback loop forces V
The input resistance
of the ADC driver, whether differential or single-ended, must be greater
than or equal to the desired termination resistance, so that a termination
resistor, R
Because the voltage
between the two amplifier inputs is driven to a null by negative feedback,
they are virtually connected, and the differential input resistance, R
Terminating a single-ended input requires significantly more effort. Figure 4 illustrates how an ADC driver operates with a single-ended input and a differential output.
Although the input
is single-ended, _{IN}.
Because resistors R_{F} and R_{G} are equal and balanced,
the gain is unity, and the differential output, V
_{OP}– V, is equal to the input, that is, 4 V p-p.
_{ON}V is equal to V_{OUT, cm}_{OCM} = 2.5 V and, from
the lower feedback circuit, input voltages V_{A+} and V_{A–}
are equal to V_{OP}/2.Using Equation 3
and Equation 4, V The general formula
for determining this single-ended input resistance when the feedback factors
of each loop are matched is shown in Equation 12, where R
This is a starting
point for calculating the termination resistance. However, it is important
to note that amplifier gain equations are based on the assumption of a
zero-impedance input source. A significant source impedance that must
be matched in the presence of an imbalance caused by a single-ended input
inherently adds resistance only to the upper R While it may be possible to determine a closed-form solution to the problem of terminating a single-ended signal, an iterative method is generally used. The need for it will become apparent in the following example. In Figure 5, a single-ended-to-differential gain of one, a 50 Ω input termination, and feedback and gain resistors with values in the neighborhood of 200 Ω are required to keep noise low. Equation 12 provides
the single-ended input resistance, 267 Ω. Equation
13 indicates that the parallel resistance, R
Figure 6 shows the circuit with source and termination resistances. The open-circuit voltage of the source, with its 50-Ω source resistance, is 2 V p-p. When the source is terminated in 50 Ω, the input voltage is reduced to 1 V p-p, which is also the differential output voltage of the unity-gain driver.
This circuit may
initially appear to be complete, but an unmatched resistance of 61.5 Ω
in parallel with 50 Ω
has been added to the upper R
With this substitution,
a 27.6-Ω resistor, R
Note that the Thévenin
voltage of 1.1 V p-p is larger than the properly terminated voltage of
1 V p-p, while the gain resistors are each increased by 27.6 Ω,
decreasing the closed-loop gain. These opposing effects tend to cancel
for large resistors The circuit in Figure 8 is now easily analyzed, and the differential output voltage is calculated in Equation 14.
The differential output voltage is not quite at the desired level of 1 V p-p, but a final independent gain adjustment is available by modifying the feedback resistance as shown in Equation 15.
Figure 9 shows the completed circuit, implemented with standard 1% resistor values.
The input resistance,
R
This differs little
from the original calculated value of 267 Ω,
and does not have a significant effect on the calculation of R If a more-exact overall gain were necessary, higher precision or series trim resistors could be used. A single iteration
of the method described here works well for closed-loop gains of one or
two. For higher gains, the value of R This should not
be arduous: Recently released differential amplifier calculator tools,
ADIsimDiffAmp
It may be useful
to recall that V
The shifted input
architecture allows the differential amplifier to process a bipolar input
signal, even when the amplifier is powered from a single supply, making
them well suited for single-supply applications with inputs at or below
ground. The additional PNP transistor (Q1 and Q4) at the input shifts
the input to the differential pair up by one transistor V Table 1 provides a quick reference to many specifications of Analog Devices ADC drivers. A glance reveals the drivers that feature a shifted ICMVR and those that do not.
An ac-coupled
For AC-coupled When input coupling is optional, it is worth noting that ADC drivers with ac-coupled inputs dissipate less power than similar drivers with dc-coupled inputs, since no dc common-mode current flows in either feedback loop. AC coupling the
ADC driver
Drivers with Systems running on dual supplies, with single-ended or differential inputs and ac- or dc-coupling, are usually fine with either type of input stage because of the increased headroom. Table 2 summarizes the most common ADC driver input-stage types used with various input-coupling and power-supply combinations. However, these choices may not always be the best; each system should be analyzed on a case-by-case basis.
For applications where every last millivolt of output voltage is required, Table 1 shows that quite a few ADC drivers have rail-to-rail outputs, with typical headroom ranging from a few millivolts to a few hundred millivolts, depending on the load.
Figure 13 shows
a plot of harmonic distortion vs. VOCM at various frequencies for the
ADA4932,
which is specified with a typical output swing to within 1.2 V of each
rail (headroom). The output swing is the sum of V
All ADCs inherently
have quantization noise, which depends on the number of bits, Quantization noise
occurs because the ADC quantizes analog signals having infinite resolution
into a finite number of discrete levels. An least
significant bit (LSB), or q, for quantum level. One quantum
level is therefore 1/2 of the converter’s range. If
a varying voltage is converted by a perfect ^{n}n-bit ADC, then converted
back to analog and subtracted from the ADC’s input, the difference will
look like noise. It will have an rms value of (Equation 21):
From this, the logarithmic
(dB) formula for the
The input signal
is The reciprocal of
THD + Noise, the
If SINAD is substituted
for the
ENOB can also be expressed in terms of SINAD as shown in Equation 26.
ENOB can be used to compare noise performance of an ADC driver with that of the ADC to determine its suitability to drive that ADC. A differential ADC noise model is shown in Figure 14.
The contributions
to the total output noise density of each of the eight sources are shown
in Equation 27 for the general case, and when β
The total output
noise voltage density, v ADC driver noise performance can now be compared with the ENOB of an ADC. An example that illustrates this procedure is to select and evaluate a differential driver with a gain of 2 for an AD9445 ADC on a 5-V supply, with a 2-V full-scale input; it is processing a direct-coupled broadband signal occupying a 50 MHz (–3-dB) bandwidth, limited with a single-pole filter. From the data-sheet listing of ENOB specifications for various conditions: for a Nyquist bandwidth of 50 MHz, ENOB = 12 bits. The ADA4939
is a high-performance broadband differential ADC driver that can be direct-coupled.
Is it a good candidate to drive the AD9445 with respect to noise? The
data sheet recommends R First, calculate
the system noise bandwidth, _{N} is equal to π/2
times the 3-dB bandwidth, as shown here (Equation 28).
Next, integrate the noise density over the square-root of the system bandwidth to obtain the output rms noise (Equation 29).
The amplitude of the noise is presumed to have a Gaussian distribution, so, using the common ±3σ limits for the peak-to-peak noise (noise voltage swings between these limits about 99.7% of the time), the peak-to-peak output noise is calculated in Equation 30.
Now compare the driver’s peak-to-peak output noise with 1 LSB voltage of the AD9445 LSB, based on an ENOB of 12 bits and full-scale input range of 2 V, as calculated in Equation 31.
The peak-to-peak output noise from the driver is comparable to the ADC’s LSB, with respect to 12 bits of ENOB; the driver is therefore a good choice to consider in this application from the standpoint of noise. The final determination must be made by building and testing the driver/ADC combination.
For example, consider the ADA4937-1 with 50 mV p-p at 60 MHz of noise on the power line. Its PSR at 50 MHz is –70 dB. This means the noise on the power supply line would be reduced to approximately 16 μV at the amplifier output. In a 16-bit system with a 1-V full-scale input, 1 LSB is 15.3 μV; the noise from the power supply line would therefore swamp the LSB. This situation can be improved by adding series SMT ferrite beads, L1/L2, and shunt bypass capacitors, C1/C2 (Figure 15).
At 50 MHz, the ferrite bead has an impedance of 60 Ω and the 10-nF (0.01-μF) capacitor has an impedance of 0.32 Ω. The attenuator formed by these two elements provides 45.5 dB of attenuation (Equation 32).
The divider attenuation combines with the PSR of –70 dB to provide about 115 dB of rejection. This reduces the noise to approximately 90 nV p-p, well below 1 LSB.
The same approach used in the noise-analysis example can be applied to distortion analysis, comparing the ADA4939’s harmonic distortion with 1 LSB of the AD9445’s ENOB of 12 bits with 2-V full-scale output. One ENOB LSB was shown to be 488 μV in the noise analysis. The distortion data
in the ADA4939 specification table is given for a gain of 2, comparing
2
The data show that harmonic distortion increases with frequency and that HD2 is worse than HD3 in the bandwidth of interest (50 MHz). Harmonic distortion products are higher in frequency than the frequency of interest, so their amplitude may be reduced by system band-limiting. If the system had a brick-wall filter at 50 MHz, only the frequencies higher than 25 MHz would be of concern, since all harmonics of higher frequencies would be eliminated by the filter. Nevertheless, we will evaluate the system up to 50 MHz, since any filtering that is present may not sufficiently suppress the harmonics, and distortion products can alias back into the signal bandwidth. Figure 16 shows the ADA4939’s harmonic distortion vs. frequency for various supply voltages with a 2 V p-p output.
HD2 at 50 MHz is approximately –88 dBc, relative to a 2-V p-p input signal. In order to compare the harmonic distortion level to 1 ENOB LSB, this level must be converted to a voltage as shown in Equation 33.
This distortion product is only 80 μV p-p, or 16% of 1 ENOB LSB. Thus, from a distortion standpoint, the ADA4939 is a good choice to consider as a driver for the AD9445 ADC. Since ADC drivers are negative feedback amplifiers, output distortion depends upon the amount of loop gain in the amplifier circuit. The inherent open-loop distortion of a negative feedback amplifier is reduced by a factor of 1/(1 + LG), where LG is the available loop gain. The amplifier’s
input (error voltage) is multiplied by a large forward voltage gain, A(s),
then passes though the feedback factor, β, to the input,
where it adjusts the output to minimize the error. Thus, the loop gain
of this type of amplifier is Current-feedback
amplifiers use an error Loop gain also depends
directly upon the feedback factor, 1/R
bandwidth of a device is used to mean the small-signal bandwidth,
while slew rate measures the maximum rate of change at the amplifier
output for large signal swings.
Figure 18 indicates that in order to maintain greater than –80 dBc for 2nd and 3rd harmonics, this ADC driver shouldn’t be used for frequencies greater than 60 MHz. Since each application is different, the system requirements will be a guide to the appropriate driver with sufficient bandwidth and adequate distortion performance.
The derivative (rate of change) of Equation 34 at the zero crossing, the maximum rate, is
Where
Therefore, when selecting an ADC driver, it is important to consider the gain, bandwidth, and slew rate (FPBW) to determine if the amplifier is adequate for the application.
Stability of a negative-voltage-feedback
amplifier depends on the magnitude and sign of its loop gain,
With unmatched feedback factors, the effective feedback factor is simply the average of the two feedback factors. When they are matched and defined as β, the loop gain simplifies to A(s) × β. For a feedback amplifier
to be stable, its loop gain must not be allowed to equal –1; or its equivalent,
an amplitude of 1 with phase shift of –180°. For a voltage feedback amplifier,
the point where the magnitude of loop gain equals 1 (that is, 0 dB) on
its open-loop gain-frequency plot is where the magnitude of A(s) equals
the reciprocal of the feedback factor. For basic amplifier applications,
the feedback is purely resistive, introducing no phase shifts around the
feedback loop. With matched feedback factors, the frequency independent
reciprocal of the feedback factor, 1 + R
Further examination
of Figure 19 shows that the ADA4932 has approximately 50°
of phase margin at a noise gain of 1 (100% feedback in each loop). While
it is not practical to operate the ADC drivers at zero gain, this observation
shows that the ADA4932 can operate stably at fractional differential gains
(R Phase margin for
The loop gain is
0 dB where the 300 Ω feedback resistance horizontal
line intersects the transimpedance magnitude curve. At this frequency,
the phase of T(s) is approximately –135°,
resulting in phase margin of 45°.
Phase margin and stability increase as R
With voltage-feedback
amplifiers, it is best to use the smallest possible R PCB layout is necessarily one of the last steps in a design. Unfortunately, it is also one of the most often overlooked steps in a design, even though high-speed circuit performance is highly dependent on layout. A high-performance design can be compromised, or even rendered useless, by a sloppy or poor layout. Although all aspects of proper high-speed PCB design can’t be covered here, a few key topics will be addressed. Parasitic elements
rob high-speed circuits of performance. Parasitic Minimizing undesired
parasitic reactances starts with keeping all traces as short as possible.
Outer layer 50-Ω PC-board traces on FR-4 contribute
roughly 2.8 pF/inch and 7 nH/inch. These parasitic reactances increase
by about 30% for inner-layer 50 Ω
traces. Also make sure there Power-supply bypassing
is another key area of concern for layout; make sure the power supply
bypass capacitors, as well as the V
Use of ground plane,
and grounding in general, is a detailed and complex subject and beyond
the scope of this article. However, there are a few key points to make,
which are illustrated in Figure 22a and Figure 22b. First, connect the
analog and digital grounds together at only one point
Refer to We hope that the material presented here has helped you think about the many considerations that must be taken into account when you design with ADC drivers. Understanding differential amplifiers—and paying attention to the details of ADC driver design at the outset of a project—will minimize problems down the road, keeping you out of the ADC driver breakdown lane.
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