Advanced Digital Post-Processing Techniques Enhance Performance in Time-Interleaved ADC Systems
While the speed and resolution of standard ADC products have advanced well beyond 4 MHz and 7 bits, time-interleaved ADC systems (for good reasons) have not advanced far beyond 8-bit resolution. Nevertheless, at 8-bit performance levels, this concept has been widely adopted in the test and measurement industry, particularly for wideband digital oscilloscopes. That it continues to make an impact in this market is evidenced by the 20-GSPS,
The primary limiting factor in time-interleaved ADC systems at 12- and 14-bit levels is the requirement that the channels be matched. An 8-bit system that provides a dynamic range of 50 dB can tolerate a gain mismatch of 0.25% and a clock-skew error of 5 ps. This level of accuracy can be achieved by traditional methods, such as matching physical channel layouts, using common ADC reference voltages, prescreening devices, and active analog trimming, but at higher resolutions the requirements are much tighter. Until now devices employing more innovative matching techniques have not been commercially available.
This article will outline in detail the matching requirements for 12- and 14-bit time-interleaved ADC systems, discuss the idea of advanced digital post-processing techniques as an enabling technology, and introduce a device employing the most promising solution to date, Advanced Filter Bank (AFB), from V Corp Technologies, Inc.5, 6
Time Interleaving Process Overview
Figure 1. Four-channel time-interleaved ADC system.
For simplicity, this article focuses primarily on two-converter systems, but four-converter systems are discussed when required to articulate key performance differences. Most of the block diagrams, mathematical relationships, and solutions will highlight the two-channel configuration.
Design Challenge of Time Interleaving
While these methods are thorough and very useful, the error voltage approach used here provides a simple method for understanding the relationship without requiring a deep study of complex mathematical derivations. This approach is based on the same philosophy used in Analog Devices Application Note AN-5019 to establish the relationship between aperture jitter and signal-to-noise (SNR) degradation in ADCs. The error voltage is defined as the difference between the expected sample voltage and the actual sample voltage. These differences are a result of a large subset of errors that fall into three basic categories: gain (Figure 2), phase (Figure 3), and offset (Figure 4) mismatches.
Figure 2. Voltage error due to gain mismatch.
Figure 3. Voltage error due to encode/clock skew.
Figure 4. Voltage error due to offset mismatch.
In a two-converter interleaved system, the error voltages generated by gain and phase mismatches result in an image spur that is located at Nyquist minus the analog input frequency. The offset mismatch generates an error voltage that results in an offset spur that is located at Nyquist. Since the offset spur is located at the edge of the Nyquist band, designers of two-channel systems can typically plan their system frequency around it, and focus their efforts on gain- and phase matching. Figure 5 displays a typical FFT plot for a two-channel system.
Figure 5. Typical two-converter interleaved FFT plot.
In a four-converter interleaving system, there are three image spurs and two offset spurs. The image spurs, generated by gain and phase mismatches between the ADC channels, are located at (1) Nyquist minus the analog input frequency and (2) one-half Nyquist plus or minus the analog input frequency. The offset spurs are located at Nyquist and at one-half of Nyquist (middle of the band). Figure 6 displays a typical FFT plot of a four-converter system, illustrating the locations of these five spurs.
Figure 6. Typical four-converter interleaved FFT plot.
Once the error voltages from each of the three mismatch groups are known, the following equations can be used to calculate the image and offset spurs (ISgain, ISphase, IStotal, OSoffset) in a single-tone, two-converter system:
As noted earlier, the gain- and phase errors generate error functions that are orthogonal7, requiring a root-sum-square combination of their individual contributions to the image spur. Using these equations, an error budget can be developed to determine what level of matching will be required to maintain a given dynamic range requirement. For example, a 12-bit dynamic range requirement of 74 dBc at an input frequency of 180 MHz would require gain matching better than 0.02% and aperture delay matching better than 300 fs! If the gain can be perfectly matched, the aperture delay matching can be relaxed to approximately 350 fs. Figure 7 displays an example of a detailed error budget curve for this 12-bit, 180-MHz example.
Figure 7. Error budget: 12-bit, 2-channel, 180-MHz input.
Table I provides the matching requirements for several different cases to illustrate the extreme precision required to make a classical time-interleaved A/D conversion system work at 12- and 14-bit resolutions over wide bandwidths.
Table I. Time-interleaved ADC matching requirements.
Traditional Approach to Wide-Bandwidth Time-Interleaved ADC Systems
Figure 8. Functional diagram of a traditional time-interleaved ADC.
Many of these matching approaches are based on careful analog design and trim techniques. While there has been an abundance of excellent ideas to address these tough matching requirements, many of them require additional circuits that add error sources of their owndefeating the original purpose of achieving precise gain and phase matching. An example of such an idea would be setting the rise and fall times of the two different clock signals. Any circuit that could provide this level of control would be subjected to increased influence of power-supply voltageand temperatureon each channels phase behavior.
Advanced Digital Post Processing
Wide bandwidth and temperature matching presents the greatest opportunityand challengefor using digital post-processing techniques to improve the performance of time-interleaving ADC systems. The mathematical derivations required for designing the digital calibration transfer functions for multiple ADC channels over wide bandwidths and temperature ranges are extremely complex and not readily available. However, a great deal of academic work has been invested in this area, creating a number of interesting solutions. One of these solutions, known as Advanced Filter Bank (AFB), stands out in its ability to provide a platform for a significant breakthrough.
Figure 9. Example of digital post-processing architecture.
Advanced Filter Bank (AFB)
Figure 10. AFB basic block diagram.
By using a unique multirate FIR filter structure, AFB can be easily implemented into a convenient digital hardware platform, such as an FPGA or CPLD. The FIR coefficients are calculated using a patented method that involves starting with the equations seen in Figure 9, and then applying a variety of advanced mathematical techniques to solve for the digital calibration transfer function.
AFB enables time-interleaving ADC systems to use up to 90% of their Nyquist band, and can be configured to operate in any Nyquist zone of the converter (e.g., first, second, third, etc.) The appropriate Nyquist zone can be selected using a set of logic inputs, which control the required FIR coefficients.
AFB Design Example
Figure 11. AD12400 block diagram.
The ADCs transfer functions are obtained using wide-bandwidth, wide-temperature range measurements during the manufacturing process. This characterization routine feeds the ADCs measured transfer functions directly into the AFB coefficient calculation process. Once the ADCs have been characterized, and the required FIR coefficients have been calculated, the FPGA is programmed and the product is ready for action. Wide bandwidth matching is achieved using AFBs special FIR structure and coefficient calculation process. Wide temperature performance is achieved by selecting one of the multiple FIR coefficient sets, using an on-board digital temperature sensor.
The true impact of this technology can be seen in Figures 12 and 13. Figure 12 displays the image-spur performance across the first Nyquist zone of this system. The first curve in Figure 12 represents the performance of a 2-channel time-interleaved system that has been carefully designed to provide optimal matching in the layout. The behavior of the image spur in this curve makes it obvious that this system was manually trimmed at an analog input frequency of 128 MHz. A similar observation of Figure 13 suggests a manual trim temperature of 40°C.
Figure 12. Performance of a manually trimmed system before and after AFB compensation
Figure 13. Performance of a manually trimmed system before and after AFB compensation over the temperature range.
Despite a careful PCB layout, tightly matched front-end circuit, tightly matched clock-distribution circuit, and common reference voltages used in the AD12400 ADC, the dynamic range degrades rapidly as the frequency and/or temperature deviates from the manual trim conditions. This rapid rate of degradation can be anticipated in any two-converter time-interleaved ADC system by analyzing some of the sensitive factors affecting this circuit. For example, the gain-temperature coefficient of a typical high-performance, 12-bit ADC is 0.02%/°C. In this case, a 10°C change in temperature would cause a 0.2% change in gain, resulting in an image spur of 60 dBc (see
By contrast, the dynamic range performance shown in these figures remains solid when the AFB compensation is enabled. In fact, the dynamic range performance surpasses the 12-bit level across a bandwidth of nearly 190 MHz and a temperature range of 40°C. Another significant advantage of this approach is that the temperature range can actually be expanded from the 20°C to 60°C range shown to 0°C to 85°C by using additional FIR coefficient setsas embodied in the AD12400.
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