OBSOLETE PRODUCT — AD7725:  16-Bit Sigma Delta ADC with a Programmable Post Processor

The AD7725 is a complete 16-bit, sigma-delta analog to digital converter with on chip user-programmable signal conditioning. The output of the modulator is processed by three cascaded finite impulse response (FIR) filters, followed by a user-programmable post processor. The user has complete control over the filter response, the filter coefficients and the decimation ratio.

The AD7725 is specified for input bandwidths up to 300 kHz and an output word rate of 600 kHz maximum. The input sample rate is set either by the crystal oscillator or an external clock, , which has a specified value of 9.6MHz and a maximum value of 14.4MHz. The CLKIN frequency directly determines the maximum input bandwidth of the device with the relationship being BW (max) = CLKIN/32. The conversion data is available via a serial or parallel interface.

To program the Post Processor, either the on-chip, default filter or a user-defined filter in the form of a configuration file can be loaded into the device. The user-defined filter can be loaded from a DSP or an external EPROM with a serial interface or from a DSP with a parallel interface.

The user-defined filter configuration file can be generated using a digital filter design package called 'Filter Wizard'. This package allows the user to design different filter types and generates the appropriate configuration file to be loaded to the device.

AD7725:  16-Bit Sigma Delta ADC with a Programmable Post Processor

製品概要

The AD7725 is a complete 16-bit, sigma-delta analog to digital converter with on chip user-programmable signal conditioning. The output of the modulator is processed by three cascaded finite impulse response (FIR) filters, followed by a user-programmable post processor. The user has complete control over the filter response, the filter coefficients and the decimation ratio.

The AD7725 is specified for input bandwidths up to 300 kHz and an output word rate of 600 kHz maximum. The input sample rate is set either by the crystal oscillator or an external clock, , which has a specified value of 9.6MHz and a maximum value of 14.4MHz. The CLKIN frequency directly determines the maximum input bandwidth of the device with the relationship being BW (max) = CLKIN/32. The conversion data is available via a serial or parallel interface.

To program the Post Processor, either the on-chip, default filter or a user-defined filter in the form of a configuration file can be loaded into the device. The user-defined filter can be loaded from a DSP or an external EPROM with a serial interface or from a DSP with a parallel interface.

The user-defined filter configuration file can be generated using a digital filter design package called 'Filter Wizard'. This package allows the user to design different filter types and generates the appropriate configuration file to be loaded to the device.

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仕様

Resolution 16bit
Number of Channels 1
ADC Sampling Rate (typ) 14.4MSPS
Output Data Format Par,Ser
沪ICP备09046653号
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