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AD9510:  1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

Product Details

Product Status:Recommended for New Designs

The AD9510 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and low phase noise in order to maximize data converter clocking performance. Four independent LVPECL and four LVDS clock outputs operate to 1.2 GHz and 800 MHz respectively. Optional CMOS clock outputs available to 250 MHz.

The PLL section consists of a programmable reference divider, R; a low-noise phase frequency detector, PFD; a precision charge pump, CP; and a programmable feedback divider, N. By connecting an external VCXO or VCO to the CLK2 and CLK2B pins, PLL output frequencies up to 1.6 GHz may be synchronized to the input reference, REFIN.

The clock distribution section provides LVPECL outputs and outputs that may be programmed to either LVDS or CMOS. Each output has a programmable divider, which may be bypassed or set to divide by any integer up to 32.

Each divider allows the user to change the phase of one clock output relative to another clock output. This phase select functions as a coarse timing adjustment. Some outputs also feature programmable delay elements with a user-selected, fullscale range to 10 ns. This fine tuning delay block is programmed with a 5-bit word, which gives the user 32 possible delays from which to choose.

The AD9510 is ideally suited for data converter clocking applications where maximum converter performance is achieved with sub-picosecond jitter encode signals.

The AD9510 is available in a 64-lead LFCSP and is specified from -40°C to +85°C. The part may be run from a single 3.3 V supply. Users wishing to extend the voltage range for external VCOs may run the charge pump supply, VCP, to 5.5V.


  • Low jitter, low phase noise clock distribution
  • Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFE™ Converters
  • Wireless infrastructure transceivers
  • High performance instrumentation
  • Broadband infrastructure


  • Phase locked loop (PLL) Core
    Reference input frequencies to 250 MHz
    Programmable dual-modulus prescaler
    Programmable charge pump (CP) current
    Separate CP supply (VCP) extends tuning range
  • Two 1.6 GHz, differential clock inputs
  • 8 programmable dividers, 1 to 32, all integers
  • Phase select for output-to-output coarse delay adjust
  • Four independent 1.2 GHz LVPECL outputs
    Additive output jitter , 225 fs RMS
  • Four independent 800 MHz/250 MHz LVDS/CMOS outputs
    Additive output jitter, 275 fs RMS
    Fine delay adjust on 2 outputs, 5-bit delay words
  • Serial control port
  • Space-saving 64-lead LFCSP

Functional Block Diagram for AD9510

Of Note ...

Two evaluation boards are available for the AD9510:
AD9510/PCB: Evaluation Board without VCO or VCXO or loop filter
AD9510-VCO/PCB: Evaluation Board with 245.76MHz VCXO, loop filter

An Overview of the Clock Distribution/Generation Family is available.


Title Content Type File Type
AD9510: 1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs Data Sheet (Rev B, 09/2013) (pdf, 592 kB) Data Sheets PDF
AN-0974: Multicarrier TD-SCMA Feasibility  (pdf, 634 kB) Application Notes PDF
AN-0983: Introduction to Zero-Delay Clock Timing Techniques  (pdf, 162 kB) Application Notes PDF
AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal  (pdf, 221 kB) Application Notes PDF
AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies)  (pdf, 170 kB) Application Notes PDF
AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance  (pdf, 313 kB) Application Notes PDF
AN-835: Understanding High Speed ADC Testing and Evaluation  (pdf, 985 kB) Application Notes PDF
AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers  (pdf, 207 kB) Application Notes PDF
AN-769: Generating Multiple Clock Outputs from the AD9540  (pdf, 0) Application Notes PDF
AN-823: Direct Digital Synthesizers in Clocking Applications Time  (pdf, 115 kB)
Jitter in Direct Digital Synthesizer-Based Clocking Systems
Application Notes PDF
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter  (pdf, 291 kB) Application Notes PDF
AN-501: Aperture Uncertainty and ADC System Performance  (pdf, 227 kB)
A Key Concern in IF Sampling is that of Aperture Uncertainty (Jitter)
Application Notes PDF
Speedy A/Ds Demand Stable Clocks
by Jeff Keip, Analog Devices, Inc. (EE Times, 3/18/04)
Technical Articles HTML
Design A Clock-Distribution Strategy With Confidence
by Demetrios Efstathiou (Electronic Design, April 27, 2006)
Technical Articles HTML
Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems
... Much of your system's performance depends on jitter specifications, so careful assessment is critical.
by Brad Brannon, Analog Devices (EDN, 12/7/2004)
Technical Articles HTML
Low-power direct digital synthesizer cores enable high level of integration Technical Articles HTML
Improved DDS Devices Enable Advanced Comm Systems
by Valoree Young, Analog Devices
(Electronic Products, September 2006)
Technical Articles HTML
ADI Buys Korean Mobile TV Chip Maker
(EE Times, 6/7/2006)
Technical Articles HTML
Clock Requirements For Data Converters
(Electronic Design, 2/2005)
Technical Articles HTML
Analog-to-Digital Converter Clock Optimization: A Test Engineering Perspective
(Analog Dialogue, Vol. 42, February 2008)
Analog Dialogue HTML
Analog-to-Digital Converter Clock Optimization: A Test Engineering Perspective  (pdf, 909 kB)
By Rob Reeder, Wayne Green, and Robert Shillito
Technical Documentation PDF
Clock-circuit-design Tool Recovers Engineer Time
(EDN, 8/23/2005)
Product Reviews HTML
Where Analog Really Meets Digital
(EE Time, 8/29/2005)
Product Reviews HTML
Circuit Simulation Tool Simplifies Clock Designs
(eeProductCenter, 8/23/2005)
Product Reviews HTML
Ultra-low Jitter Performance Marks Analog Devices' Entry into the Clock IC Market
(eeProductCenter, 12/8/04)
Product Reviews HTML
Analog Devices’ Dual 14-bit A/D Converter Reduces Power and Size in Communications, Instrumentation, Test and Measurement Applications (10 Jul 2012) Press Releases HTML
RF Source Booklet  (PDF, 4353 kB)
RF IC Product Overview - Version P (02/2014)
Overview PDF
Multi-Output Clock Generators Overview HTML
Expanding Family of Integrated Clock ICs Overview HTML
Leading Inside Advertorials: Single-Chip Clock Generator with 14-Channel Distribution Solves Timing Challenges in Networks  (pdf, 64 kB) Overview PDF
Reset your thinking about clocks.  (pdf, 153 kB)
... In precision timing, analog is everywhere.
Overview PDF
Clock and Timing ICs  (pdf, 4970 kB) Overview PDF
Why do I see reference spurs? FAQs/RAQs HTML
Why is my phase noise shape changing when I change the PLL settings? FAQs/RAQs HTML
Why doesn't the PLL make my reference input and the clock outputs line up? FAQs/RAQs HTML
How do I optimize my PLL loop for the best phase noise and/or jitter? FAQs/RAQs HTML
My loop is not locking. How do I debug this? FAQs/RAQs HTML
How long does it take for the PLL to lock? FAQs/RAQs HTML
Help! My PLL came unlocked over temperature. FAQs/RAQs HTML
How do I choose between active and passive filter in PLL loop? FAQs/RAQs HTML
Should I reference the passive filter to ground? or supply? FAQs/RAQs HTML
How do the PLLs in the AD951x parts compare to other ADI PLLs? FAQs/RAQs HTML
How does the clock clean-up function of the AD951x parts work? FAQs/RAQs HTML
Why do I want to run a fast PFD frequency? FAQs/RAQs HTML
Is it ok for me to connect the same power supply to both the charge pump and distribution power supply pins? FAQs/RAQs HTML
Why can't I use a bandpass filter for my loop filter? FAQs/RAQs HTML
Should I tie my loop filter to ground or PLL supply? FAQs/RAQs HTML
The loop filter was working great until I changed the divide ratio in PLL. What happened? FAQs/RAQs HTML
How do I use a VCO with a supply greater than 5V? FAQs/RAQs HTML
What suppliers do you recommend for VCO/VCXOs? FAQs/RAQs HTML
Do VCXOs have better phase noise and jitter performance than VCOs? FAQs/RAQs HTML
How do I know which VCO will work best with the AD9510? FAQs/RAQs HTML
Is there an advantage to running a higher VCO frequency than the output frequency? FAQs/RAQs HTML
How do I determine if a VCO is good enough for my purpose? FAQs/RAQs HTML
Is there any difference between the nature of an oscillator's phase noise and the phase noise from a clock chip? FAQs/RAQs HTML
Do different divide ratios cause variations in jitter? FAQs/RAQs HTML
I have a clocking scheme which requires several different division ratios simultaneously. I have a frequency plan, but I'm concerned about crosstalk. How much of a problem is this with your clock distribution chips? FAQs/RAQs HTML
Do divide ratios change the propagation delay? FAQs/RAQs HTML
I want to use the phase offset feature on the AD9510 dividers to generate two signals 90° out of phase. How accurate is the phase offset? FAQs/RAQs HTML
On the AD951x clock ICs, does the phase offset (coarse delay) affect the jitter? FAQs/RAQs HTML
Why doesn't the mini-divider support the divide ratio I want? FAQs/RAQs HTML
I want to use the variable delay adjust, but the jitter is too high. What can I do? FAQs/RAQs HTML
I changed the coarse phase adjust in the evaluation software, but nothing happened. What's going on? FAQs/RAQs HTML
What is the difference between the coarse phase adjust and the fine delay adjust? FAQs/RAQs HTML
What is the fine delay adjust which is available on certain LVDS/CMOS outputs? FAQs/RAQs HTML
Does the fine delay adjust affect the jitter? FAQs/RAQs HTML
Why is the fine delay adjust not available on all the outputs? FAQs/RAQs HTML
Is there a way to cause Input/Output rising edges to be synchronous (zero delay) with the AD9510/11? FAQs/RAQs HTML
Will the AD9510 work without a reference input signal? FAQs/RAQs HTML
What are the best clock sources for a distribution-only design? FAQs/RAQs HTML
I am not using the CLK1 input on the AD9510. Can I just leave it floating? FAQs/RAQs HTML
How good does my input signal need to be? FAQs/RAQs HTML
I turned off my reference but the Digital Lock Detect (DLD) still says I'm locked. FAQs/RAQs HTML
Can I shift the threshold on clocks for single-ended inputs? FAQs/RAQs HTML
The reference input is differential, but my reference is single-ended. Do I need to convert to differential to drive the AD9510? FAQs/RAQs HTML
Will differential or single-ended inputs/outputs improve my jitter? FAQs/RAQs HTML
Why should I use differential rather than single-ended? FAQs/RAQs HTML
How do I feed a single-ended signal into a differential input? FAQs/RAQs HTML
Why do you recommend AC coupling, rather than DC coupling, at the clock inputs? FAQs/RAQs HTML
Are the ADI clock parts stand-alone clock sources or do I still have to buy a clock source to drive these parts? FAQs/RAQs HTML
Which provides better performance - a clock source with sinewave output, or one with differential square wave outputs? FAQs/RAQs HTML
On the AD9510, what is the relationship between clock output jitter and CLK1/CLK2 input slew rate? FAQs/RAQs HTML
I'm trying to write to the part in single-byte mode, but I can't write anything. What am I doing wrong? FAQs/RAQs HTML
Can I use the 951X clocks to drive a mixer (RF LO)? FAQs/RAQs HTML
My applications are RF, not for clocking data converters. Can ADI's 951X ICs be used for RF applications? FAQs/RAQs HTML
I have an input present at the clock input, but I'm not seeing an output? FAQs/RAQs HTML
What happens to the AD9510/11 clock outputs if the Reference Input (REFIN) signal goes away? FAQs/RAQs HTML
What clock frequency comes out of the AD9510 outputs when you first apply power to the device? FAQs/RAQs HTML
Is it possible to impedance match a clock output if it is heavily loaded? (e.g. CL=100pF) FAQs/RAQs HTML
I ran the AD9510 outputs at 1.4 GHz and they seem to work fine. Is there a problem running them at 1.4 GHz? FAQs/RAQs HTML
What should I do with unused channels on the AD9510? FAQs/RAQs HTML
Can I tri-state the AD9510 outputs? FAQs/RAQs HTML
On the AD9510, how can I make sure that the duty cycle of output clocks stays within 40% to 60% duty cycle window? FAQs/RAQs HTML
What is the effect of distributing harmonically related clocks (on chip or on board) in terms of jitter? FAQs/RAQs HTML
Is there any reason to use a transformer on a differential clock output to obtain a "clean" single-ended clock output? FAQs/RAQs HTML
What are some of the advantages/disadvantages of using LVPECL vs. LVDS outputs? FAQs/RAQs HTML
Does the AD9510 support 2.5V PECL? FAQs/RAQs HTML
How much bandwidth is required to process a PECL or LVDS output? FAQs/RAQs HTML
If I use only one of the PECL differential outputs and the unused output is terminated in 50Ω, how will this affect the phase noise or jitter of the single-ended output? FAQs/RAQs HTML
If I change the level of PECL output, does it affect the jitter? FAQs/RAQs HTML
What is the best way to terminate LVPECL outputs to get lowest jitter? FAQs/RAQs HTML
Is it okay to AC-couple PECL or LVDS outputs? FAQs/RAQs HTML
What is the fan-out capability of the CMOS, LVDS, and LVPECL outputs? FAQs/RAQs HTML
What is the proper termination (value and location) for outputs? FAQs/RAQs HTML
Are outputs short-circuit protected? FAQs/RAQs HTML
Are the CMOS drivers on the clock devices complementary? FAQs/RAQs HTML
Some of the schematics in the AD951x data sheets show an LVPECL termination scheme which is different from the classic termination often seen (50 Ω to Vs - 2V, or the Thevenin equivalent thereof). How does this work, and how did you chose 200 Ω for the resistors? Can I use 100 ohms to improve the slew rate (or jitter)? FAQs/RAQs HTML
I have pulled SYNCB low, but I still have output from a channel. Why? FAQs/RAQs HTML
Why can I not get the same output amplitude or rise and fall times as stated in your datasheet? FAQs/RAQs HTML
The AD9510 datasheet says to use an external pull-up resistor on the FUNCTION pin. Why do I need this and what range of resistors will work? FAQs/RAQs HTML
May I use the AD9540 for spread spectrum clocking? FAQs/RAQs HTML
Can I get two clock outputs from the AD9540? FAQs/RAQs HTML
What's the advantage of a DDS-based clock generator? FAQs/RAQs HTML
Why does the AD9540 require special filtering on its analog output. What are the requirements of this filter? FAQs/RAQs HTML
I'm working with optical networks - SONET/SDH. Do ADI's clock chips support these applications? FAQs/RAQs HTML
On my board, I can't get the same low jitter numbers that are shown in the datasheet. Am I doing something wrong? FAQs/RAQs HTML
How do you determine the bandwidth over which phase noise is integrated to obtain jitter? FAQs/RAQs HTML
Using the "ADC SNR method", what is the equivalent bandwidth for the jitter specification? FAQs/RAQs HTML
How do harmonic spurs in the output spectrum affect jitter (random or deterministic)? FAQs/RAQs HTML
When a jitter number is specified without an associated bandwidth, what bandwidth should be assumed? FAQs/RAQs HTML
How do you specify jitter? FAQs/RAQs HTML
How do I use the clock part for jitter clean-up? FAQs/RAQs HTML
If jitter can be calculated from phase noise measurements, is it possible to calculate phase noise from jitter numbers? FAQs/RAQs HTML
Does jitter vary with different clock frequencies? How about phase noise? FAQs/RAQs HTML
I sure can't measure jitter with femtosecond resolution on my scope! How do you do it? How much confidence do you have in the jitter figures that you are quoting for these parts? FAQs/RAQs HTML
Do you guarantee performance shown in ADIsimCLK? FAQs/RAQs HTML
Who do I contact for technical support on ADIsimCLK? FAQs/RAQs HTML
Should I use the minimum charge pump current settings in order to minimize power? FAQs/RAQs HTML
Can I run CMOS outputs at 5V? FAQs/RAQs HTML
Can I use different power supply voltages for the PECL output drivers? FAQs/RAQs HTML
Is .01 uF sufficient for power supply pin bypass? FAQs/RAQs HTML
My application has pretty tight power consumption requirements. I am very interested in the capabilities of the AD9510, but I don't need every feature. Is it possible to turn off the unused features and save power? FAQs/RAQs HTML
Why don't you spec psrr and cmrr in the datasheet? FAQs/RAQs HTML
How do I get two AD951x (with PLL) to synchronize to the same reference input edge? FAQs/RAQs HTML
I really need >10 clock outputs. Can I use multiple chips together and still guarantee that all output clocks are synchronized to REFIN? FAQs/RAQs HTML
How do I synchronize multiple clock devices? FAQs/RAQs HTML
What happens if I run the part in an ambient environment which exceeds 85°C? FAQs/RAQs HTML
How can I determine the die temperature of your device? FAQs/RAQs HTML
My circuit board has both an analog GND and a digital GND. How should I connect the AD9510 pins labeled GND? FAQs/RAQs HTML
What PCB layout recommendations do you have for the of the exposed paddle on the bottom side of the LFCSP package? FAQs/RAQs HTML
RAQs index Rarely Asked Questions HTML
Glossary of EE Terms Glossary HTML

Design Tools,Models,Drivers & Software

Title Content Type File Type
ADIsimCLK Design and Evaluation Software
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
ADIsim Design/Simulation Tools HTML
AD9510 IBIS Models IBIS Models HTML

Evaluation Kits & Symbols & Footprints

Evaluation Boards & KitsView the Evaluation Boards and Kits page for documentation and purchasing

Symbols and Footprints— Analog Devices offers Symbols & Footprints which are compatible with a large set of today’s CAD systems for broader and easier support.

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Price, packaging, availability

Price Table Help

The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.

AD9510 Evaluation Board
Model Description Price RoHS View PCN/ PDN Check Inventory/
AD9510/PCBZ Status: Contact ADI Evaluation Board $190.00 Yes -
AD9510-VCO/PCBZ Status: Contact ADI Evaluation Board $190.00 Yes -

Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.

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