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AD6620:  65MSPS Digital Receive Signal Processor

Analog Devices' innovative Diversity Receiver chipset delivers two IF-to-baseband diversity channels in a compact, comprehensive solution that incorporates Automatic Gain Control, Received Signal Strength Indicator, high-resolution. Numerically Controlled Oscillator and digital filtering on-chip.

The chipset comprises Analog Devices' AD6600 dual-channel IF sampling analog-to-digital ...More

AD6620:  65MSPS Digital Receive Signal Processor

Product Description

Analog Devices' innovative Diversity Receiver chipset delivers two IF-to-baseband diversity channels in a compact, comprehensive solution that incorporates Automatic Gain Control, Received Signal Strength Indicator, high-resolution. Numerically Controlled Oscillator and digital filtering on-chip.

The chipset comprises Analog Devices' AD6600 dual-channel IF sampling analog-to-digital converter and AD6620 dual-channel decimating receiver chip. Configured with the appropriate external components, it can address a variety of air interface standards, including GSM, CDMA, IS136 and PHS, as well as proprietary modulation schemes for paging systems and wireless fixed access receivers.

Based on Analog Devices' next-generation receiver architecture, the Diversity Receiver replaces sensitive analog filters with digital filters for significant cost and size reductions. Complete reference designs show the optimal layout for reducing noise and minimizing cross-channel coupling.

RESOURCES & TOOLS

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  • High Input Sample Rate
    67 MSPS Single Channel Real
    33.5 MSPS Diversity Channel Real
    33.5 MSPS Single Channel Complex
  • NCO Frequency Translation
    Worst Spur Better than –100 dBc
    Tuning Resolution Better than 0.02 Hz
  • 2nd Order Cascaded Integrator Comb FIR Filter
    Linear Phase, Fixed Coefficients
    Programmable Decimation Rates: 2, 3 . . . 16
  • 5th Order Cascaded Integrator
    Comb FIR Filter
    Linear Phase, Fixed Coefficients
    Programmable Decimation Rates:
    1, 2, 3 . . . 32
  • Programmable Decimating RAM
    Coefficient FIR Filter
    Up to 134 Million Taps per Second
    256 20-Bit Programmable Coefficients
    Programmable Decimation Rates:
    1, 2, 3 . . . 32
  • Digital TX/RX: RX
  • Input Sampling (MSPS): 65MSPS
  • Baseband Interface: Parallel,Serial
  • Input Ports: 1
  • Ouput Ports: 1
  • Package: MQFP

Functional Block Diagram for AD6620

AD6620 Diagram
Functional Block Diagram for AD6620
Download this Selection Table
(pdf, 22,589 bytes)

Last Updated: 9/2007
DDCs
Generic Part # MSPS GSM, EDGE/GPRS CDMA2000 UMTS TDS-CDMA
      1x 3x    
AD6620 65

1 Channel

(main and diversity)

1 Channel

2 samples per chip

1 Channel with FPGA to finish filtering

2 samples per chip

1 Channel with FPGA to finish filtering

2 samples per chip

 1 Channel
AD6624 80

4 Channels

2 samples per symbol

2 Channels

2 samples per chip

1 Channel with FPGA for serial to parallel conversion

2 samples per chip

1 Channel with FPGA for serial to parallel conversion

2 samples per chip

 4 Channels

1 sample per chip
AD6624A 100

2 Channels with FPGA for serial to parallel conversion

2 samples per chip
AD6634 80

4 Channels

2 samples per symbol

2 Channels

4 samples per chip

Digital AGC

2 Channels

4 samples per chip

Digital AGC

2 Channels

4 samples per chip

Digital AGC

4 Channels

1 sample per chip
AD6635 80

8 Channels

2 samples per symbol

4 Channels

4 samples per chip

Digital AGC

4 Channels

4 samples per chip

Digital AGC

4 Channels

4 samples per chip

Digital AGC

8 Channels

1 sample per chip
AD6636 150

6 Channels

4 / 8 samples per symbol

6 Channels

4 samples per chip

Digital AGC

6 Channels

4 samples per chip

Digital AGC

6 Channels

4 samples per chip

Digital AGC

6 Channels

1 / 2 / 4 samples per chip
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DUCs
Generic Part # MSPS GSM, EDGE/GPRS CDMA2000 UMTS TDS-CDMA
      1x 3x    
AD6622

75

4 Channels

Serial output

2 Channels

Serial output

1 Channel

Serial output

1 Channel

Serial output

4 Channels

Serial output
AD6623 104

4 Channels

Modulate using I/Q symbols

Direct modulation xPSK

Mode switching

Power Ramping

2 Channels (real output)

Serial output

Includes IIR filter for phase pre-distortion

2 Channels (real output)

Serial output

2 Channels (real output)

Serial output

4 Channels

Serial output

Power Ramping

Direct modulation
AD6633 125

6 Channels

Modulated I/Q data

VersaCREST™ Crest Reduction Engine

IF/RF compensation using complex filter

6 Channels

Modulated I/Q data

VersaCREST™ Crest Reduction Engine

Includes IIR filter for phase pre-distortion

6 Channels

Modulated I/Q data

VersaCREST™ Crest Reduction Engine

IF/RF compensation using complex filter

6 Channels

Modulated I/Q data

VersaCREST™ Crest Reduction Engine

IF/RF compensation using complex filter

6 Channels

Modulated I/Q data

VersaCREST™ Crest Reduction Engine

IF/RF compensation using complex filter
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Integrated ADC/DDC Receivers
Generic Part # MSPS GSM, EDGE/GPRS CDMA2000 UMTS TDS-CDMA
      1x 3x    
AD6652 65

4 Channels

2 samples per symbol

2 Channels with some external filtering

4 samples per chip

Digital AGC

2 Channels with some external filtering

4 samples per chip

Digital AGC

2 Channels with some external filtering

4 samples per chip

Digital AGC

4 Channels

1 sample per chip
AD6653 150

2 x 6 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 12 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 6 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 4 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 12 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor
AD6654 92.16

6 Channels

4 / 8 samples per symbol

6 Channels

4 samples per chip

Digital AGC

6 Channels

4 samples per chip

Digital AGC

6 Channels

4 samples per chip

Digital AGC

6 Channels

1 / 2 / 4 samples per chip
AD6655 150

2 x 6 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 12 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 6 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 4 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor

2 x 12 Channels - external Channelization Filters Required

Fast Level Detect and Power Monitor
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QDUCs
Generic Part # Master Clock (MSPS min) Power Supply Voltage (Vnom) Power Dissipation (mW max) Description
AD9856 200 Single (+3) 1590 200 MHz Quadrature Digital Upconverter With 12-Bit Data Path
AD9857 200 Single (3.3 V) 2029 200 MSPS Quadrature Digital Upconverter with 14-bit Data Path
AD9957 1000 Multi (1.8, 3.3) 1800 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC
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Pricing, Packaging & Availability

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For detailed drawings and chemical composition please consult our  Package Site

Pin Count
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  • Commercial: 0 to +70 degrees Celsius
  • Military : -55 to +125 degrees Celsius
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  • Automotive: -40 to +125 degrees Celsius
Price
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*The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.
**Sample availability may be better than production availability. Please enter samples into your cart to check sample availability.