Two Selectable Inputs, 12 LVPECL Outputs, SiGe Clock Fanout Buffer
The ADCLK954 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter.
The device has two selectable differential inputs via the IN_SEL control pin. Both inputs are equipped with center tapped, differential, 100 Ω on-chip termination resistors. The inputs accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREFx pin is available for biasing ac-coupled inputs.
The ADCLK954 features 12 full-swing emitter coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias Vcc to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply.
The output stages are designed to directly drive 800 mV each side into 50 Ω terminated to VCC − 2 V for a total differential output swing of 1.6 V.
The ADCLK954 is available in a 40-lead LFCSP and specified for operation over the standard industrial temperature range of −40°C to +85°C.
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
This page contains evaluation board documentation and ordering information for evaluating the ADCLK954.
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Solutions Bulletins & Brochures
Digital-to-Analog Converter ICs Solutions Bulletin, Volume 10, Issue 1
Design A Clock-Distribution Strategy With Confidence
by Demetrios Efstathiou (Electronic Design, April 27, 2006)
Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems
... Much of your system's performance depends on jitter specifications, so careful assessment is critical.
Termination of High-Speed Converter Clock Distribution Devices
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