Six LVPECL Outputs, SiGe Clock Fanout Buffer
The device has a differential input equipped with center-tapped, differential, 100 Ω on-chip termination resistors. The input accepts dc-coupled LVPECL, CML, 3.3 V CMOS (single ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREF pin is available for biasing ac-coupled inputs.
The ADCLK946 features six full-swing emitter-coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply.
The ECL output stages are designed to directly drive 800 mV each side into 50 Ω terminated to VCC − 2 V for a total differen-tial output swing of 1.6 V.
The ADCLK946 is available in a 24-lead LFCSP and is specified for operation over the standard industrial temperature range of −40°C to +85°C.
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
The ADCLK946 is a very high performance clock fanout buffer. The evaluation board is fabricated using a high quality Rogers dielectric material. Transmission line paths are kept as close to 50 Ω as possible.
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Digital-to-Analog Converter ICs Solutions Bulletin, Volume 10, Issue 1
Design A Clock-Distribution Strategy With Confidence
by Demetrios Efstathiou (Electronic Design, April 27, 2006)
Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems
... Much of your system's performance depends on jitter specifications, so careful assessment is critical.
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