1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
There are three independent clock outputs. Two of the outputs are LVPECL, and the third output can be set to either LVDS or CMOS levels. The LVPECL outputs operate to 1.6 GHz, and the third output operates to 800 MHz in LVDS mode and to 250 MHz in CMOS mode.
Each output has a programmable divider, which can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to another clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment.
The LVDS/CMOS output features a delay element with three selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each with 16 steps of fine adjustment.
The AD9514 does not require an external controller for operation or setup. The device is programmed by means of 11 pins (S0 to S10) using 4-level logic. The programming pins are internally biased to ⅓ VS. The VREF pin provides a level of ⅔ VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.
The AD9514 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter.
The AD9514 is available in a 32-lead LFCSP and operates from a single 3.3 V supply. The temperature range is −40°C to +85°C.
- Low jitter, low phase noise clock distribution
- Clocking high speed ADC, DAC, DDS, DDC, DUC, MxFE
- High performance wireless transceivers
- High performance instrumentation
- Broadband infrastructure
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This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Analog-to-Digital Converter Clock Optimization: A Test Engineering Perspective
(Analog Dialogue, Vol. 42, February 2008)
ADIsimCLK™ Reference Design Files
Once ADIsimCLK is installed, users may take advantage of saved design files with the extension, ".clk".
Design A Clock-Distribution Strategy With Confidence
by Demetrios Efstathiou (Electronic Design, April 27, 2006)
Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems
... Much of your system's performance depends on jitter specifications, so careful assessment is critical.
Low-power direct digital synthesizer cores enable high level of integration
Improved DDS Devices Enable Advanced Comm Systems
by Valoree Young, Analog Devices
(Electronic Products, September 2006)
ADI Buys Korean Mobile TV Chip Maker
(EE Times, 6/7/2006)
Clock Requirements For Data Converters
(Electronic Design, 2/2005)
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
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