High Speed, Low Power, 4-channel Simultaneous Sampling, 12-Bit ADC
Any subset of the four channels can be converted to maximize the throughput rate on the selected sequence. Select the channels to convert via hardware (channel select input pins) or software (programming the channel select register).
A single conversion start signal (CONVST) simultaneously places all the track-and-holds into hold and initiates a conversion sequence for the selected channels. The EOC signal indicates the end of each individual conversion in the selected conversion sequence. The BUSY signal indicates the end of the conversion sequence.
Data is read from the part by a 12-bit parallel data bus using the standard CS and RD signals. Maximum throughput for a single channel is 500 kSPS. For all four channels, the maximum throughput is 130 kSPS for the read-during-conversion sequence operation. The throughput rate for the read-after-conversion sequence operation depends on the read cycle time of the processor. See the Timing and Control section. The AD7864 is available in a small (0.3 square inch area) 44-lead MQFP.
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
Compensate for Loading Effects on Power Lines with a DSP-Controlled Active...
(Analog Dialogue, Vol. 33, No. 9, October, 1999)
MS-2210: Designing Power Supplies for High Speed ADC
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