AD6636
NOT RECOMMENDED FOR NEW DESIGNS150 MSPS Wideband (Digital) Receive Signal Processor (RSP)
- Part Models
- 2
- 1ku List Price
- Starting From $49.83
Overview
- Six Independent Wideband Processing Channels
- Processes 6 Wideband carriers (UMTS, CDMA2000, TD-SCDMA, etc.)
- Four Single Ended or Two LVDS Parallel Input Ports (16 linear bit plus 3-bit exponent) at 150 MHz
- Can support 300MHz input using some external interface logic
- Three 16-bit Parallel Output Ports operating at up to 200 MHz
- Real or complex input ports
- Quadrature correction andDC correction for complex inputs
- Can support output rate up to 34 MSPS
- RMS/Peak Power monitoring of input ports
- Programmable attenuator control for external Digital Variable Gain Amplifier (DVGA)
- Three Programmable coefficient FIR Filters per channel
- One Interpolating Half Band Filter per channel
The AD6636 is a (Digital) Receive Signal Processor intended for direct IF sampling or highly sampled baseband radios requiring wide-bandwidth input signals. It has been optimized for the demanding filtering requirements of wideband standards like, CDMA2000, UMTS, and TD-SCDMA. The AD6636 is designed to be used as part of radio system that uses either an IF sampling ADC, or a baseband sampling ADC.
The AD6636 has the following signal processing stages: a Frequency Translator, a 5th order Cascaded Integrated Comb filter, two sets of Cascaded Fixed Coefficient Finite Impulse Response (FIR) and Half Band filters, three cascaded programmable coefficient Sum of Product FIR filters, an Interpolating Half Band Filter (LHB) and a digital Automatic Gain Control (AGC) Block. Multiple modes are supported for clocking data into and out of the chip to provide flexibility for interfacing to a wide variety of digitizers. Programming and control is accomplished via serial or microport interfaces.
The AD6636 features a fractional clock multiplier that uses the ADC clock to produce a digital down converter master clock up to 200 MHz. This internal phased-locked loop (PLL) allows optimum digital clock rates, regardless of the converter sampling rate, enabling the best possible digital signal decimation and filtering. Three 16-bit parallel output ports accommodate high data rate 3G applications. An on-chip interpolating half band filter can also be used to further increase the output rate while still allowing for very efficient filters. In addition, each channel has a digital AGC for output data scaling.Documentation
Data Sheet 1
Application Note 4
Technical Articles 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD6636BBCZ | 256-Ball CSPBGA (17mm x 17mm) | ||
| AD6636CBCZ | 256-Ball CSPBGA (17mm x 17mm) |
| Part Models | Product Lifecycle | PCN |
|---|---|---|
|
Mar 16, 2011 - 10_0105 Conversion to Laser Marking for the BGA Packages (Single Grades) |
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| AD6636BBCZ | ||
| AD6636CBCZ | ||
This is the most up-to-date revision of the Data Sheet.