The ADP5040 combines one high performance buck regulator and two low dropout regulators (LDO) in a small 20-lead LFCSP to meet demanding performance and board space requirements.
The high switching frequency of the buck regulator enables the use of tiny multilayer external components and minimizes board space.
When the MODE pin is set to logic high, the buck regulator operates in forced pulse width modulation (PWM) mode. When the MODE pin is set to logic low, the buck regulator operates in PWM mode when the load is around the nominal value. When the load current falls below a predefined threshold the regulator operates in power save mode (PSM) improving the light-load efficiency. The low quiescent current, low dropout voltage, and wide input voltage range of the ADP5040 LDOs extend the battery life of portable devices. The ADP5040 LDOs maintain a power supply rejection greater than 60 dB for frequencies as high as 10 kHz while operating with a low headroom voltage.
Each regulator in the ADP5040 is activated by a high level on the respective enable pin. The output voltages of the regulators are programmed though external resistor dividers to address a variety of applications.
|Title||Content Type||File Type|
|ADP5040: Micro PMU with 1.2A Buck Regulator and Two 300 mA LDOs Data Sheet (Rev A, 01/2014) (pdf)||Data Sheets|
|Multi-output Regulators with Supervisory and Watchdog Timers Reduce Component Count, Increase Power Density and Reliability (23 Jan 2012)||Press Releases||HTML|
Integrated Power Solutions for Xilinx FPGAs
(pdf, 2253 kB)
Combining multiple switching regulators and LDOs into a single package enables very small, flexible, highly efficient power management solutions for powering FPGAs.
|Integrated Power Solutions for Altera FPGAs (pdf, 2460 kB)||Solutions Bulletins|
|RAQs index||Rarely Asked Questions||HTML|
|Glossary of EE Terms||Glossary||HTML|
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