ADSP-2104L

Obsolete

16-bit, 13 MIPS, 3.3v, 2 serial ports

Data Sheet (Rev. 0) Product Selection Table
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Overview

  • 20 MIPS, 50 ns Maximum Instruction Rate
  • Wired and Wireless Voice
  • Separate On-Chip Buses for Program and Data Memory
  • VoIP/VoN
  • Optical Networking
  • Program Memory Stores Both Instructions and Data (Three-Bus Performance)
  • Dual Data Address Generators with Modulo and Bit-Reverse Addressing
  • Speech Recognition
  • Efficient Program Sequencing with Zero-Overhead Looping: Single-Cycle Loop Setup
  • Modems
  • Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory (e.g., EPROM )
  • Test and Measurement
  • Double-Buffered Serial Ports with Companding Hardware, Automatic Data Buffering, and Multichannel Operation
  • Industrial Control
  • Three Edge- or Level-Sensitive Interrupts
  • Low Power IDLE Instruction
  • PLCC Package

The ADSP-2104 and ADSP-2109 processors are single-chip microcomputers optimized for digital signal processing (DSP) and other high speed numeric processing applications. The ADSP-2104/ADSP-2109 processors are built upon a common core. Each processor combines the core DSP architecture- computation units, data address generators, and program sequencer- with differentiating features such as on-chip program and data memory RAM (ADSP-2109 contains 4K words of program ROM), a programmable timer, and two serial ports.

Fabricated in a high speed, submicron, double-layer metal CMOS process, the ADSP-2104/ADSP-2109 operates at 20 MIPS with a 50 ns instruction cycle time. The ADSP-2104L and ADSP-2109L are 3.3 volt versions which operate at 13.824 MIPS with a 72.3 ns instruction cycle time. Every instruction can execute in a single cycle. Fabrication in CMOS results in low power dissipation.

ADSP-2104L
16-bit, 13 MIPS, 3.3v, 2 serial ports
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Documentation

Data Sheet 1

Application Note 10

Processor Manual 1

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Software Resources

Software & Tools Anomaly 1

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