The AD6636 is a (Digital) Receive Signal Processor intended for direct IF sampling or highly sampled baseband radios requiring wide-bandwidth input signals. It has been optimized for the demanding filtering requirements of wideband standards like, CDMA2000, UMTS, and TD-SCDMA. The AD6636 is designed to be used as part of radio system that uses either an IF sampling ADC, or a baseband sampling ADC.
The AD6636 has the following signal processing stages: a Frequency Translator, a 5th order Cascaded Integrated Comb filter, two sets of Cascaded Fixed Coefficient Finite Impulse Response (FIR) and Half Band filters, three cascaded programmable coefficient Sum of Product FIR filters, an Interpolating Half Band Filter (LHB) and a digital Automatic Gain Control (AGC) Block. Multiple modes are supported for clocking data into and out of the chip to provide flexibility for interfacing to a wide variety of digitizers. Programming and control is accomplished via serial or microport interfaces.
The AD6636 features a fractional clock multiplier that uses the ADC clock to produce a digital down converter master clock up to 200 MHz. This internal phased-locked loop (PLL) allows optimum digital clock rates, regardless of the converter sampling rate, enabling the best possible digital signal decimation and filtering. Three 16-bit parallel output ports accommodate high data rate 3G applications. An on-chip interpolating half band filter can also be used to further increase the output rate while still allowing for very efficient filters. In addition, each channel has a digital AGC for output data scaling.
|Title||Content Type||File Type|
|AD6636: 150 MSPS, Wideband, Digital Downconverter (DDC) Data Sheet (Rev A, 06/2005) (pdf, 1133 kB)||Data Sheets|
|AN-807: Multicarrier WCDMA Feasibility (pdf, 969 kB)||Application Notes|
AN-808: Multicarrier CDMA2000 Feasibility
(pdf, 1535 kB)
The goal of this application note is to determine the feasibility of implementing a multicarrier CDMA2000 transceiver and what the major subsystem performances must be.
|AN-835: Understanding High Speed ADC Testing and Evaluation (pdf, 985 kB)||Application Notes|
|AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (pdf, 262 kB)||Application Notes|
Design A Clock-Distribution Strategy With Confidence
by Demetrios Efstathiou (Electronic Design, April 27, 2006)
|RAQs index||Rarely Asked Questions||HTML|
|Glossary of EE Terms||Glossary||HTML|
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