The AD6649 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital downconverter (DDC) and a bypass-able sample rate converter (SRC). The AD6649 is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired.
The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.
ADC data outputs are internally connected directly to the digital downconverter (DDC) of the receiver. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO), an optional sample rate converter, a fixed FIR filter, and an fs/4 fixed-frequency NCO.
In addition to the receiver DDC, the AD6649 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.
After digital processing, data is routed directly to the 14-bit output port. These outputs operate at 1.8 V LVDS signal levels.
The AD6649 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. In diversity applications the output data format is real due to the final NCO which shifts the output center frequency to fs/4.
Flexible power-down options allow significant power savings, when desired.
Programming for setup and control is accomplished using a 3-pin SPI-compatible serial interface.
The AD6649 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.APPLICATIONS
|Title||Content Type||File Type|
|AD6649: IF Diversity Receiver Data Sheet (Rev B, 01/2013) (pdf, 1083 kB)||Data Sheets|
|AN-1142: Techniques for High Speed ADC PCB Layout (pdf, 392 kB)||Application Notes|
|AN-878: High Speed ADC SPI Control Software (pdf, 585 kB)||Application Notes|
|AN-282: Fundamentals of Sampled Data Systems (pdf, 2131 kB)||Application Notes|
|AN-737: How ADIsimADC Models an ADC (pdf, 373 kB)||Application Notes|
|AN-807: Multicarrier WCDMA Feasibility (pdf, 969 kB)||Application Notes|
AN-808: Multicarrier CDMA2000 Feasibility
(pdf, 1535 kB)
The goal of this application note is to determine the feasibility of implementing a multicarrier CDMA2000 transceiver and what the major subsystem performances must be.
|AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (pdf, 203 kB)||Application Notes|
|AN-877: Interfacing to High Speed ADCs via SPI (pdf, 1594 kB)||Application Notes|
|AN-905: VisualAnalog Converter Evaluation Tool Version 1.0 User Manual (pdf, 2124 kB)||Application Notes|
|AN-935: Designing an ADC Transformer-Coupled Front End (pdf, 363 kB)||Application Notes|
|AN-835: Understanding High Speed ADC Testing and Evaluation (pdf, 985 kB)||Application Notes|
AN-586: LVDS Outputs for High Speed A/D Converters
(pdf, 207 kB)
High Speed ADCs Uses LVDS (Low-Voltage Differential Signaling) to Minimize Performance Limitations In ADC Applications When Providing High Speed Data Output
AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit (pdf, 452,449 bytes)
(pdf, 441 kB)
This application note describes the operation of a general-purpose, microcontroller-based Serial Port Interface (SPI) boot circuit.
|AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (pdf, 262 kB)||Application Notes|
|AN-742: Frequency Domain Response of Switched-Capacitor ADCs (pdf, 401 kB)||Application Notes|
|AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated (pdf, 370 kB)||Application Notes|
AN-345: Grounding for Low-and-High-Frequency Circuits
(pdf, 455 kB)
Know Your Ground and Signal Paths for Effective Designs. Current Flow Seeks Path of Least Impedance-Not Just Resistance....
|AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (pdf, 291 kB)||Application Notes|
AN-501: Aperture Uncertainty and ADC System Performance
(pdf, 227 kB)
A Key Concern in IF Sampling is that of Aperture Uncertainty (Jitter)
|AN-741: Little Known Characteristics of Phase Noise (pdf, 1679 kB)||Application Notes|
|UG-293: Evaluating the AD9643/AD9613/AD6649/AD6643 Analog-to-Digital Converters (pdf, 2740 kB)||User Guides|
|High-speed Data Converters and IF Diversity Receivers From ADI Maximize Receiver Sensitivity and Dynamic Range for 3G and 4G Cellular Base Stations (26 May 2011)||Press Releases||HTML|
|Glossary of EE Terms||Glossary||HTML|
|Title||Content Type||File Type|
ADIsimADC is Analog Devices' Analog-to-Digital Behavioral Model that accurately models the typical performance characteristics of many of our High Speed Converters. The model faithfully reproduces the errors associated with both static and dynamic features such as AC linearity, clock jitter, and many other product specific anomalies.
|ADIsim Design/Simulation Tools||HTML|
|AD6649 IBIS Model||IBIS Models||HTML|
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