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AD6649:  IF Diversity Receiver

Product Details

Product Status:Recommended for New Designs

The AD6649 is a mixed-signal intermediate frequency (IF) receiver consisting of dual 14-bit, 250 MSPS ADCs and a wideband digital downconverter (DDC) and a bypass-able sample rate converter (SRC). The AD6649 is designed to support communications applications where low cost, small size, wide bandwidth and versatility are desired.

The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

ADC data outputs are internally connected directly to the digital downconverter (DDC) of the receiver. The digital receiver has two channels and provides processing flexibility. Each receive channel has four cascaded signal processing stages: a 32-bit frequency translator (numerically controlled oscillator (NCO), an optional sample rate converter, a fixed FIR filter, and an fs/4 fixed-frequency NCO.

In addition to the receiver DDC, the AD6649 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.

After digital processing, data is routed directly to the 14-bit output port. These outputs operate at 1.8 V LVDS signal levels.

The AD6649 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of the main channel and the diversity channel. This IF sampling architecture greatly reduces component cost and complexity compared with traditional analog techniques or less integrated digital methods. In diversity applications the output data format is real due to the final NCO which shifts the output center frequency to fs/4.

Flexible power-down options allow significant power savings, when desired.

Programming for setup and control is accomplished using a 3-pin SPI-compatible serial interface.

The AD6649 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.

APPLICATIONS
  • Communications
  • Diversity radio systems
  • Multimode digital receivers (3G)
    TD-SCDMA, WiMax, WCDMA,
    CDMA2000, GSM, EDGE, LTE
  • General-purpose software radios
  • Broadband data applications

PRODUCT HIGHLIGHTS

  1. Integrated dual, 14-bit, 250 MSPS ADC.
  2. Integrated wideband decimation filter and 32-bit complex NCO.
  3. Fast overrange and threshold detect.
  4. Proprietary differential input maintains excellent SNR performance for input frequencies up to 300 MHz.
  5. SYNC input allows synchronization of multiple devices.
  6. 3-pin, 1.8V SPI port for register programming and register readback.

FEATURES and BENEFITS

  • SNR = 73.0 dBFS in a 95 MHz BW at 185 MHz Ain and
    245.76 MSPS
  • SFDR = 85 dBc at 185 MHz Ain and 250 MSPS
  • -151.2 dBFS/Hz Input Noise @ 220 MHz, -1dBFS Ain and 250MSPS
  • Total Power consumption: 1W
  • 1.8 V analog and LVDS output supply operation
  • Integer 1-to-8 input clock divider (625Mhz maximum input)
  • Integrated dual-channel ADC
    -- Sample rates up to 250 MSPS
    -- IF sampling frequencies to 400 MHz
    -- See datasheet for additional features
  • Integrated wideband digital downconverter (DDC)
    -- 32-bit complex, numerically controlled oscillator (NCO)
    -- Sample Rate Converter and FIR filter with two modes
    -- Real Output from an fs/4 output NCO
  • Fast detect bits for efficient AGC implementation
  • Energy-saving power-down modes
  • Decimated Interleaved ‘Real’ LVDS Data Outputs

Functional Block Diagram for AD6649

Sample Availability

This product is released to manufacturing. Please contact the High Speed Converters Development Group for sample availability and additional technical information.

Documentation

Title Content Type File Type
AD6649: IF Diversity Receiver Data Sheet (Rev C, 01/2014) (pdf, 1083 kB) Data Sheets PDF
AN-1142: Techniques for High Speed ADC PCB Layout  (pdf, 392 kB) Application Notes PDF
AN-878: High Speed ADC SPI Control Software  (pdf, 585 kB) Application Notes PDF
AN-282: Fundamentals of Sampled Data Systems  (pdf, 2131 kB) Application Notes PDF
AN-737: How ADIsimADC Models an ADC  (pdf, 373 kB) Application Notes PDF
AN-807: Multicarrier WCDMA Feasibility  (pdf, 969 kB) Application Notes PDF
AN-808: Multicarrier CDMA2000 Feasibility  (pdf, 1535 kB)
The goal of this application note is to determine the feasibility of implementing a multicarrier CDMA2000 transceiver and what the major subsystem performances must be.
Application Notes PDF
AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs  (pdf, 203 kB) Application Notes PDF
AN-877: Interfacing to High Speed ADCs via SPI  (pdf, 1594 kB) Application Notes PDF
AN-905: VisualAnalog Converter Evaluation Tool Version 1.0 User Manual  (pdf, 2124 kB) Application Notes PDF
AN-935: Designing an ADC Transformer-Coupled Front End  (pdf, 363 kB) Application Notes PDF
AN-835: Understanding High Speed ADC Testing and Evaluation  (pdf, 985 kB) Application Notes PDF
AN-586: LVDS Outputs for High Speed A/D Converters  (pdf, 207 kB)
High Speed ADCs Uses LVDS (Low-Voltage Differential Signaling) to Minimize Performance Limitations In ADC Applications When Providing High Speed Data Output
Application Notes PDF
AN-812:  MicroController-Based Serial Port Interface (SPI) Boot Circuit (pdf, 452,449 bytes)  (pdf, 441 kB)
This application note describes the operation of a general-purpose, microcontroller-based Serial Port Interface (SPI) boot circuit.
Application Notes PDF
AN-851: A WiMax Double Downconversion IF Sampling Receiver Design  (pdf, 262 kB) Application Notes PDF
AN-742: Frequency Domain Response of Switched-Capacitor ADCs  (pdf, 401 kB) Application Notes PDF
AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated  (pdf, 370 kB) Application Notes PDF
AN-345: Grounding for Low-and-High-Frequency Circuits  (pdf, 455 kB)
Know Your Ground and Signal Paths for Effective Designs. Current Flow Seeks Path of Least Impedance-Not Just Resistance....
Application Notes PDF
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter  (pdf, 291 kB) Application Notes PDF
AN-501: Aperture Uncertainty and ADC System Performance  (pdf, 227 kB)
A Key Concern in IF Sampling is that of Aperture Uncertainty (Jitter)
Application Notes PDF
AN-741: Little Known Characteristics of Phase Noise  (pdf, 1679 kB) Application Notes PDF
UG-293: Evaluating the AD9643/AD9613/AD6649/AD6643 Analog-to-Digital Converters  (pdf, 2740 kB) User Guides PDF
Glossary of EE Terms Glossary HTML

Design Tools,Models,Drivers & Software

Title Content Type File Type
ADIsimADC
ADIsimADC is Analog Devices' Analog-to-Digital Behavioral Model that accurately models the typical performance characteristics of many of our High Speed Converters. The model faithfully reproduces the errors associated with both static and dynamic features such as AC linearity, clock jitter, and many other product specific anomalies.
ADIsim Design/Simulation Tools HTML
AD6649 IBIS Model IBIS Models HTML

Evaluation Kits & Symbols & Footprints

Evaluation Boards & KitsView the Evaluation Boards and Kits page for documentation and purchasing

Symbols and Footprints— Analog Devices offers Symbols & Footprints which are compatible with a large set of today’s CAD systems for broader and easier support.

Product Recommendations & Reference Designs

Companion Products

Suggested Companion Products


Recommended Driver Amplifiers for the AD6649
  • For differential RF/IF, we recommend the ultra low distortion ADL5562.
  • For a fully differential input and output DVGA in digital communications systems, we recommend the ADL5202 or the AD8376.
Recommended Clock Drivers for the AD6649
  • For low jitter performance and integrated VCO, we recommend one of the AD9520-0 or AD9522-0 family of selectable VCO frequencies.
  • For low jitter performance along with on chip PLL and VCO, we recommend the AD9523, AD9523-1 or the AD9524.
Recommended Power Solutions

  • For selecting voltage regulator products, use ADIsimPower.

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Price, packaging, availability

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The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.

AD6649 Evaluation Board
Model Description Price RoHS View PCN/ PDN Check Inventory/
Purchase/Sample
AD6649EBZ Status: Production Evaluation Board $300.00 Yes -

Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.

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