The AD9861 is a member of the MxFE® family, a group of integrated converters for the communications market. The AD9861 includes dual 10-bit Analog-to-Digital Converters (ADCs) and dual 10-bit Digital-to-Analog Converters (TxDAC® converters). Two speed grades are available, a -50 and -80. The -50 is optimized for ADC sampling of 50 MSPS and less, while the -80 is optimized for ADC sample rates between 50 MSPS and 80 MSPS. The dual TxDAC converters operate at speeds up to 200 MHz and includes a bypassable 2x or 4x interpolation filter. Three auxiliary converters are also available to provide required system level control voltages or monitor system signals. All devices are optimized for low power, small form factor and provide a cost effective solution for the broadband communication market.
The AD9861 uses a single input clock pin (CLKIN) to generate all system clocks. The ADCs and TxDAC Converters clock are generated within a timing generation block which utilizes user programmable options such as divide circuits, PLL multiplier and switches.
A Flexible bi-directional 20-bit I/O bus is used to accommodate a variety of custom digital back ends or open market DSPs. In half duplex systems, the interface supports 20-bit parallel transfers or 10-bit interleaved transfers. In Full duplex systems, the interface supports an interleaved 10-bit ADC bus and an interleaved 10-bit Tx bus. The flexible I/O bus reduces pin count and therefore required package size.
The AD9861 can use either mode pins or a serial programmable interface (SPI) to configure the interface bus, operate the ADC in a low power mode, configure the TxDAC converter interpolation rate, control the ADC power down and TxDAC power down. The SPI allows for more programmable options for both the TxDAC path (for example, coarse and fine gain control, offset control for channel matching) and ADC path (for example, internal duty cycle stabilizer, 2’s complement data format).
The AD9861 is packaged in a 64-pin lfCSP package (low profile, fine pitch chip scale package). The 64-pin lfCSP package footprint is only 9 mm by 9 mm and is less than 0.9 mm high fitting into tightly spaced applications such as PCMCIA cards.
|Title||Content Type||File Type|
|AD9861: Mixed-Signal Front-End (MxFE) Processor For Broadband Applications Data Sheet (Rev 0, 11/2003) (pdf, 1282 kB)||Data Sheets|
|AN-928: Understanding High Speed DAC Testing and Evaluation (pdf, 4445 kB)||Application Notes|
EE-236: Real-Time Solutions Using Mixed-Signal Front-End Devices with the Blackfin® Processor
(pdf, 149 kB)
|MS-2210: Designing Power Supplies for High Speed ADC (pdf, 327 kB)||Technical Articles|
|RAQs index||Rarely Asked Questions||HTML|
|Glossary of EE Terms||Glossary||HTML|
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|AD9861 IBIS Models||IBIS Models||HTML|
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