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AD6673:  80 MHz Bandwidth, Dual IF Receiver

Product Details

Product Status:Recommended for New Designs

For more information on JESD204 go to www.analog.com/jesd204.

The AD6673 is an 11-bit, 250 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.

The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic, and each ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the SPI. With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6673 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution.

The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 250 MSPS, the AD6673 can achieve up to 76.3 dBFS SNR for a 55 MHz bandwidth in the 22% mode and up to 73.5 dBFS SNR for a 82 MHz bandwidth in the 33% mode.

When the NSR block is disabled, the ADC data is provided directly to the output at a resolution of 11 bits. The AD6673 can achieve up to 65.9 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6673 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are required.

By default the ADC output data is routed directly to the two external JESD204B serial output lanes. These outputs are at current mode logic (CML) voltage levels. Two modes are supported such that output coded data is either sent through one lane or two (L = 1; F = 4 or L = 2; F = 2). Single lane operation supports converter rates up to 125 MSPS. Synchronization input controls (SYNCINB± and SYSREF±) are provided.

PRODUCT HIGHLIGHTS

  1. The configurable JESD204B output block with an integrated phase-locked loop (PLL) to support up to 5 Gbps per lane with up to two lanes.
  2. IF receiver includes two, 11-bit, 250 MSPS ADCs with programmable noise shaping requantizer (NSR) function that allows for improved SNR within a reduced bandwidth of 22% or 33% of the sample rate.
  3. Support for an optional RF clock input to ease system board design.
  4. Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz.
  5. An on-chip integer, 1-to-8 input clock divider and SYNC input allows synchronization of multiple devices.
  6. Operation from a single 1.8 V power supply.
  7. Standard serial port interface (SPI) that supports various product features and functions, such as controlling the clock DCS, power-down, test modes, voltage reference mode, over range fast detection, and serial output configuration.
APPLICATIONS
  • Diversity radio systems
  • Multimode digital receivers (3G)
    TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE
  • DOCSIS 3.0 CMTS upstream receive paths
  • HFC digital reverse path receivers
  • I/Q demodulation systems
  • Smart antenna systems
  • Electronic test and measurement equipment
  • RADAR receivers
  • COMSEC radio architectures
  • IED detection/jamming systems
  • General-purpose software radios
  • Broadband data applications

FEATURES and BENEFITS

  • JESD204B Subclass 0 or Subclass 1 coded serial digital outputs
  • Signal-to-noise ratio (SNR) = 71.9 dBFS at 185 MHz AIN and 250 MSPS with NSR set to 33%
  • Spurious-free dynamic range (SFDR) = 88 dBc at 185 MHz AIN and 250 MSPS
  • Total power consumption:
    707 mW at 250 MSPS
  • 1.8 V supply voltages
  • Integer 1-to-8 input clock divider
  • Sample rates of up to 250 MSPS
  • IF sampling frequencies of up to 400 MHz
  • Internal analog-to-digital converter (ADC) voltage reference
  • See data sheet for additional features

Functional Block Diagram for AD6673

JESD204

Design Tools,Models,Drivers & Software

Title Content Type File Type
AD6673 Evaluation Board, ADC-FMC Interposer & Xilinx KC705 Reference Design FPGA HDL HTML

Evaluation Kits & Symbols & Footprints

Evaluation Boards & KitsView the Evaluation Boards and Kits page for documentation and purchasing

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Price, packaging, availability

AD6673 Model Options
Price Table Help

The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.

AD6673 Evaluation Board
Model Description Price RoHS View PCN/ PDN Check Inventory/
Purchase/Sample
AD6673-250EBZ Status: Production Evaluation Board $300.00 Yes -
High Speed ADC FMC Interposer
Model Description Price RoHS View PCN/ PDN Check Inventory/
Purchase/Sample
CVT-ADC-FMC-INTPZB Status: Production Evaluation Board $99.00 Yes -

Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.

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