The AD6673 is an 11-bit, 250 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.
The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic, and each ADC features a wide bandwidth switched capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.
Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the SPI. With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6673 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution.
The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 250 MSPS, the AD6673 can achieve up to 76.3 dBFS SNR for a 55 MHz bandwidth in the 22% mode and up to 73.5 dBFS SNR for a 82 MHz bandwidth in the 33% mode.
When the NSR block is disabled, the ADC data is provided directly to the output at a resolution of 11 bits. The AD6673 can achieve up to 65.9 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6673 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are required.
By default the ADC output data is routed directly to the two external JESD204B serial output lanes. These outputs are at current mode logic (CML) voltage levels. Two modes are supported such that output coded data is either sent through one lane or two (L = 1; F = 4 or L = 2; F = 2). Single lane operation supports converter rates up to 125 MSPS. Synchronization input controls (SYNCINB± and SYSREF±) are provided.
|Title||Content Type||File Type|
|AD6673: 80 MHz Bandwidth, Dual IF Receiver Data Sheet (Rev B, 12/2013) (pdf, 1769 kB)||Data Sheets|
|UG-493: Quick Start Guide for Testing the AD9250/AD6673 Analog-to-Digital Converters (ADCs) Evaluation Boards Using the HSC-ADC-EVALDZ FPGA-Based Capture Board (pdf, 650 kB)||User Guides|
|Analog Devices Simplifies High-Speed Data Converter-to-FPGA Interconnect Design Environment (08 Oct 2012)||Press Releases||HTML|
|Glossary of EE Terms||Glossary||HTML|
|Title||Content Type||File Type|
|AD6673 Evaluation Board, ADC-FMC Interposer & Xilinx KC705 Reference Design||FPGA HDL||HTML|
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