LT8653S

Demonstration circuit 2535A is a 42V, dual channel, 2A synchronous step-down regulator featuring the LT8653S. The LT8653S is a compact, high efficiency, high speed synchronous monolithic step-down switching regulator which features the second generation Silent Switcher^® technology that minimizes EMI and reduces PCB layout sensitivity. The demo board is designed for two outputs: 5V and 3.3V from a 5.5V to 42V input. Each output can source up to 2A continuous current at the same time. The wide input range allows a variety of input sources, such as automotive batteries and industrial supplies. The integrated power switches and other necessary circuitry reduce the external component count and simplify design. Selectable spread spectrum mode of operation can further improve EMI/EMC performance. Ultralow quiescent current in Burst Mode^® operation achieves high efficiency at very light loads.

The DC2535A demo board is 3" by 3" in size and has four layers with 2oz copper on the outer layers and 1oz copper on the inner layers. The DC2535A operates at 2MHz switching frequency by default to minimize solution size. The LT8653S is assembled in a small thermally enhanced 4mm × 3mm LQFN package. The IC temperature rises about 50°C when both channels operate at full load, 2A each, with the default switching frequency of 2MHz.

The jumper JP2 on the demo board determines the configuration of the SYNC pin of the LT8653S. By default, the SYNC pin on the demo board is grounded for low ripple Burst Mode operation. Moving JP2 to FCM W/SSM enables the spread spectrum mode of operation by tying the SYNC pin to VCC pin. To synchronize to an external clock, move JP2 to FCM W/O SSM OR SYNC position and apply the external clock on the SYNC turret.

The jumpers JP3 and JP4 on the demo board determine the configuration of the output voltage select bit pins D0 and D1. On the DC2535A, the D0 and D1 pins are by default floating. This combination connects internal feedback resistor divider between the FB1/FB2 pins and the error amplifier which means that FB1 and FB2 pins are regulated to 5V and 3.3V respectively. On the DC2535A, FB1/FB2 pins are by default connected through 0Ω resistors to the output nodes. Refer to the LT8653S data sheet for more information on the D0 and D1 pin settings.

The demo board has an EMI filter installed. The EMI performance of the demo board (with EMI filter) is shown in Figure 1 and Figure 2. The black lines in Figure 2 are CISPR 25 class 5 limits. To achieve EMI/EMC performance as shown in Figure 2, the input EMI filter is required and the input voltage should be applied at VEMI terminal.

The LT8653S data sheet gives a complete description of the part, operation and application information. The data sheet must be read in conjunction with this manual for demo circuit 2535A.

• 32 Channel Analog Phased Array Prototyping Platform
• 8x ADAR1000 Analog Phased Array Beamforming ICs
• 32x ADTR Transmit/Receive ICs
• RF In, RF Out Design
• Individual RFIO for each BFIC
• 10 GHz Lattice Spacing
• Stand-Alone RF Detector/ADC Combo for Calibration
• PMOD and SDP Connectors for Programming
• On-Board Power Regulation from Single 12V Power Adapter (Included)

• X Band (RF) to C Band (IF) up/down converter
• 4 TX/RX RF Input/Output via SMA
• 4 TX IF Inputs via SMPM
• 4 RX IF Output via SMPM
• External LO or Internal PLL Options
• PMOD Connector for Programming
• Interposer Board via PMOD to allow SDP and FMC Connectors for Programming
• On-Board Power Regulation from Single 12V Power Adapter (Included)

• Mates with Xilinx ZCU102 Evaluation Board (Not Included)
• 4x RF Receive (Rx) Channels (8x Digital Rx Channels)
• Total 4x 12-bit 4GSPS ADC
• 8x Digital Down Converters (DDCs), Each Including Complex Numerically-Controlled Oscillators (NCOs)
• 8x Programmable Finite Impulse Response Filters (pFIRs)
• 4x RF Transmit (Tx) Channels (8x Digital Tx Channels)
• Total 4x 16-bit 12GSPS DAC
• 8x Digital Up Converters (DUCs), Each Including Complex Numerically-Controlled Oscillators (NCOs)
• Flexible Clock Distribution
• On-Board Clock Distribution from Single External 500MHz Reference
• Support for External Converter Clock
• On-Board Power Regulation Powered by ZCU102 Evaluation Board via FMC Connector

• MATLAB System Applications GUI
• Example HDL Builds including JESD204b/JESD204c Bring-Up
• Embedded Software Solutions for Linux and Device Drivers

• Hybrid Beamsteering Capability
• System Phase Calibration

The X-Band Development Platform contains one MxFE^® software defined, direct RF sampling transceivers, X-Band to C-Band Up/Down Converter, and a X/Ku Band analog phased array proto-typing platform. The target application is phased array radars, electronic warfare, and ground-based SATCOM, specifically a X Band 32 transmit/32 receive channel hybrid beamforming phased array radar.

The X-Band Development Platform highlights a complete system solution. It is intended as a testbed for demonstrating hybrid beamforming phased array radar as well as the implementation of system level calibrations, beamforming algorithms, and other signal processing algorithms. The system is designed to mate with a ZCU102 Evaluation Board from Xilinx®, which features the Zynq^® UltraScale+^™ MPSoC FPGA, with provided reference software, HDL code, and MATLAB system-level interfacing software.

The system can be used to enable quick time-to-market development programs for applications like:

• ADEF (Phased-Array, RADAR, EW, SATCOM)
• Hybrid Beamforming
• Electronic Test and Measurement