Read other articles in this series.

• 電源回路のループの安定性と補償方法について理解する【Part 1】基本的な概念、利用可能なツール

• 電源回路のループの安定性と補償方法について理解する【Part 2】異常／問題のあるボーデ線図

×

Figure 1

   

要約

Part 3 of this article series explains a simple method for designing loop compensation in current-mode controlled switch-mode power supplies. This control architecture is extensively used in power management solutions, including many of ADI’s power products. It enables the use of a simple Type 2 compensation network to design and optimize the supply feedback loop, ensuring rapid transient responses and robust stability margins. This article introduces fundamental loop design concepts, offers clear explanations of the Type 2 compensation network, and examines the role of each compensation component. The loop design process is then streamlined into three straightforward steps. Additionally, the LTpowerCAD® design tool further simplifies the loop design and optimization process.

Introduction—Basic Concepts

Switch-mode power supplies are extensively used in modern electronic systems to achieve high efficiency and power density. For less experienced system engineers, power supply loop compensation design optimization can be a critical yet challenging task. Most of ADI’s switch-mode regulators employ current-mode control architecture to achieve high performance and high reliability. For example, Figure 1 shows the basic feedback loop block diagram of a popular current-mode control step-down buck converter.¹ This architecture features an inner current sensing loop and an outer output voltage regulation loop. The inner current sense loop forces the inductor current to follow the compensation network output voltage at the ITH node. In this way, conceptually the inductor becomes a current source controlled by the voltage loop error amplifier output V_ITH. Consequently, the buck converter power stage including the current loop behaves as a single-pole system at lower frequencies below the current loop bandwidth. Therefore, a simple Type 2 compensation network is adequate to optimize supply loop stabilities and transient performances. The example Type 2 compensation network is shown in Figure 1 as the R_TH, C_TH, and C_THP network on the error op amp output ITH pin.

Figure 2 shows the conceptual power supply loop gain diagram. K_REF is the feedback resistor-divider network gain from supply output V_O to the FB pin. A(s) is the voltage loop compensation error amplifier network gain from the FB pin to the ITH pin. G_CV(s) is the power stage transfer function from error amplifier output node V_ITH to power supply output voltage Vo, including the inner current loop. Therefore, the total power supply loop gain T(s) is given by Equation 1:

Switching Power Supply Loop Design and Optimization Goals

An optimized power supply loop should be designed with high loop bandwidth to achieve fast transient response while maintaining sufficient stability margins. Furthermore, for a switching power supply, it is important to attenuate the switching noises in the feedback loop to minimize switching waveform jitters. In summary, here are key supply loop design targets:

1. Loop bandwidth (f_BW): While high loop bandwidth is generally desirable for fast transient response, it is practically limited by the switching frequency (f_SW). Typically, the maximum bandwidth is set up to 1/10 or 1/5 of f_SW.
2. Phase margin: A phase margin greater than 45° is usually required, with a margin greater than 60° phase margin being recommended.
3. Gain margin: Gain margin, defined as the gain attenuation where the loop phase is –180°, should be at least 8 dB to 10 dB.
4. Switching noise attenuation margin: For a current-mode control switching supply, it is important to attenuate switching noises in the feedback loop to minimize jittering of the switching node waveform. Practically, greater than 8 dB attenuation at f_SW/2 is preferred.

Intuitive Understanding of Type 2 Compensation Network

To design and optimize the compensation network, a power supply designer first needs to understand the effect of each compensation R or C value on the loop gain and load transient response. Figure 3 shows the Type 2 compensation network, including a typical transconductance error amplifier (that is, a voltage-controlled current source) with a gain of g_m, the amplifier parasitic output resistance R₀, and the compensation network including R_TH, C_TH, and C_THP. These three key ITH pin R/C components are to adjust the compensation gain A(s) and therefore determine the supply loop gain bandwidth, stability margins, and transient response performances.

The compensation gain A(s) is defined as shown in Equation 2.

Since the internal g_m and R₀ are fixed for a given controller IC, the impedance of the R_TH, C_TH, and C_THP network Z_ITH (s) determines the compensation gain A(s). Detailed equation derivations are given in ADI application note AN149 (see Equation 3): ¹

where

For power supply designers, instead of memorizing this A(s) equation, the compensation gain should be understood in an intuitive way by observing how the Z_ITH impedance changes vs. the frequency shown in the conceptual plot in Figure 4.

Figure 4 conceptual plot can be explained below from left to right, as the frequency increases from lower to higher values through the following ranges:

Range 1: From DC to low frequency pole f_P1, all capacitors are treated as open circuits with high impedance. Therefore, the Z_ITH magnitude is determined by the error amplifier parasitic output resistance R_O, which is usually a very large value (~MΩ). In this range, the error amplifier A(s) has a flat high DC gain equal to g_m × R₀.

Range 2: As the frequency increases, the first C_TH capacitor impedance drops (note that C_TH>>C_THP, so the C_THP impedance is still very high). At frequency f_P1, the C_TH impedance magnitude is comparable to R_O. After f_P1, as the frequency further increases, the C_TH impedance determines the total Z_ITH impedance.

Range 3: As the frequency further increases, the C_TH impedance magnitude eventually drops to the value close to the R_TH value in the series path. After that, the R_TH value dominates the total Z_ITH value and keeps it flat in this range. The corner frequency where the C_TH and R_TH impedance values are close to each other is defined as the zero frequency f_Z1. The target supply loop bandwidth f_BW is usually set within frequency range 3

Range 4: As the frequency increases even more, eventually the smaller parallel C_THP impedance drops to the value comparable to the R_TH value. After that, the Z_ITH magnitude is determined by the C_THP impedance. The corner frequency where the R_TH and C_THP impedance are close is defined as the second HF pole f_P2. When needed, this high frequency pole should be located below the supply switching frequency fSW to attenuate switching noises.

With this explanation, it shows the Z_ITH impedance amplitude is determined by each different R or C component at different frequency ranges. This observation helps us to understand the effect of each component on the supply loop gain and transient response.

How Does Each Compensation Component Affect Loop Gain and Transient Response?

(1) Compensation Resistor R_TH

Usually, the compensation network is designed so that the power supply loop bandwidth f_BW is located between zero f_Z1 and pole f_P2 in frequency range 3. In this range, the Z_ITH magnitude is determined by the R_TH value. So, the R_TH value directly determines the power supply loop bandwidth f_BW. Figure 5 illustrates that the increased R_TH value can increase the compensation gain A(s) between f_Z1 and f_P1. Therefore, larger R_TH leads to higher loop bandwidth, as shown in Figure 6a. Higher loop bandwidth usually can reduce supply V_OUT undershoot and overshoot amplitude during load transient, as shown in Figure 6b, without much change in the V_OUT settling time after a transient event.

(2) Compensation Capacitor C_TH

In a typical design, the compensation capacitor C_TH should only affect loop gain in frequency range 2 between f_P1 and f_Z1. Figure 7 shows a smaller C_TH value (with higher impedance) increases the A(s) gain in frequency range 2. Figure 8 shows that smaller C_TH does not affect the supply loop bandwidth and, therefore, does not change much of the V_OUT undershoot and overshoot amplitude during a load transient event. However, a smaller C_TH helps to reduce transient settle time, thanks to its higher gain in the lower frequency range 2.

(3) Compensation Capacitor C_THP

C_THP is usually a smaller high frequency, low ESR, and low ESL capacitor to attenuate high frequency noises in the feedback loop. Therefore, the power supply has a clean and low jitter switching waveform. It can be helpful for current-mode supplies that are sensitive to noises on their current comparator inputs. C_THP should be selected to be much less than C_TH and contribute its effect only in high frequency (range 4). For the supply loop gain, C_THP can help to achieve the desired >8 dB attenuation at f_SW/2. Figure 9 shows how increased C_THP helps to reduce A(s) gain at higher frequencies. Figure 10 shows that increased C_THP reduces the supply loop gain at higher frequencies, so high frequency noises can be attenuated. As long as C_THP is kept as a small value (<<C_TH), the loop bandwidth and load transient responses are not affected.

Simple 3-Step Loop Compensation Design Process

With a good and intuitive understanding of the Z_ITH network, the Type 2 compensation design can be done in a simple, 3-step process for a given target loop bandwidth. It can be done with the LTpowerCAD supply design tool or with bench bode plot measurement equipment.

Step 1—Setting the R_TH Value for the Target Loop Bandwidth

Conceptually, the R_TH value can be directly calculated for a given target loop bandwidth f_BW from Equation 1. At the loop bandwidth (cross-over frequency), the loop gain magnitude is 0 dB, which is 1:

Therefore, the R_TH value can be derived in the following steps:

Practically, if it is not convenient to estimate the G_CV value with a typical controller IC, ADI’s LTpowerCAD program can be used instead. LTpowerCAD is a complete power supply design tool supporting power stage and loop compensation optimizations.2 On the LTpowerCAD loop design page, users can preset a very large C_TH value first, then start with a small R_TH and increase it gradually until the target loop bandwidth is achieved. In this case, with current-mode control, the phase margin is preferred to be greater than 60°. If not, simply reduce the R_TH value back to reduce the loop bandwidth until the desired 60° phase margin is achieved. See Figure 11.

Without using LTpowerCAD, if bode plot measurement equipment is used in the lab, a designer can still start using a large C_TH value then increase R_TH from very small to large until the desired loop bandwidth and phase margin is achieved in measurement.

Step 2—Setting the C_THP Value to Attenuate Noises

Next, using the LTpowerCAD tool or bode plot measurement, C_THP should be increased from 0 until the loop gain at f_SW/2 is below –8 dB for switching noise attenuation. In addition, the supply gain margin (at phase margin = 0) should be 8 dB to 10 dB as well. See Figure 12.

Step 3—Set the C_TH Value for Fast Transient Settle Time

In this step, decrease the very high preset C_TH value until the supply’s phase margin starts to drop noticeably, which means f_Z1 is approaching the loop bandwidth. Smaller C_TH helps to reduce load transient settle time. However, if C_TH is too small, eventually the supply phase margin will be affected. Maintain the 45° to 60° phase margin. See Figure 13.

(Optional) Step 4—Additional Phase Boost from Resistor Divider Capacitors

In case adjusting C_TH, C_THP, and R_TH still cannot achieve the desired loop bandwidth and stability margins, the resistor divider network can be further adjusted by adding the feedforward capacitor C_FF and filter capacitor C_FLT. The goal is to achieve a phase boost around the targeted loop bandwidth, usually with the help of C_FF. This can be done on the LTpowerCAD loop compensation page by opening the Feedback tab. Figure 14 shows good and bad examples of designing the R-divider capacitors. The good example maximizes phase boost at the target loop bandwidth frequency.

Further Simplification Using LTpowerCAD One-Click Loop Design

To further simplify the loop design effort, ADI’s LTpowerCAD program provides a one-click automatic loop compensation design function based on the 3-step method explained in this article. As shown in Figure 15, a user can set the target loop bandwidth, which is usually in the range of 1/10 to 1/5 of the switching frequency, then click on the Use Suggested Compensation checkbox. The LTpowerCAD program will provide a set of R_TH, C_TH, and C_THP values to achieve the targeted loop bandwidth with a good phase margin. If the target bandwidth or phase margin is not achievable, the user should reduce the target loop bandwidth frequency. This one-click loop design function can be disabled by unchecking the Use Suggested Compensation box to allow users to manually design and fine tune loop and load transient performances.

Conclusion

For a switching power supply utilizing a popular current-mode control architecture, loop compensation design and optimization can be easily accomplished using the straightforward and simple 3-step method outlined in this article. The LTpowerCAD design tool provides real-time results, and its one-click automatic loop design function greatly simplifies the design and optimization process.

References

¹ Henry Zhang. “AN-149: Modeling and Loop Compensation Design of Switch-Mode Power Supplies.” Analog Devices, Inc., January 2015.

² Henry Zhang. “AN-158F: Designing Power Supply Parameters in Five Simple Steps with the LTpowerCAD Design Tool.” Analog Devices, Inc., September 2015.

Zhang, Henry. “Understand Power Supply Loop Stability and Loop Compensation—Part 1: Basic Concepts and Tools.” Analog Devices, Inc., January 2022.

Zhang, Henry. “Understanding Power Supply Loop Stability and Compensation—Part 2: Unusual or Problematic Bode Plots.” Analog Devices, Inc., June 2024.

著者について

Henry Zhang

Henry Zhangは、アナログ・デバイセズの技術フェロー／シニア・アプリケーション・ディレクタです。2001年にLinear Technology（現在はアナログ・デバイセズに統合）に入社しました。1994年に中国の浙江大学で電気工学の学士号、1998年と2001年にバージニア工科大学（バージニア州ブラックスバーグ）で電気工学の修士号と博士号をそれぞれ取得しています。