AN-1323: High Performance Digital MEMS Microphone Simple Interface to SigmaDSP Audio Codec
Circuit Function and Benefits
The circuit shown in Figure 1 allows up to two digital microelectromechanical systems (MEMS) microphones to be interfaced to an audio codec. The ADMP421 consists of a MEMS microphone element, an output amplifier, and a fourth-order, Σ-Δ modulator. Digital MEMS microphones output data in a pulse density modulated (PDM) bit stream that is immune to noise and crosstalk issues that may degrade the performance of an analog microphone connection. In small form factor applications such as mobile phones, digital cameras, or portable navigation devices, where isolating sensitive audio signal paths may not be possible, a digital MEMS microphone signal path provides flexibility in microphone and codec placement and layout.
Figure 1. Digital MEMS Microphone Connection to Audio Codec (Simplified Schematic: Power Supply Decoupling and All Connections Not Shown).
Up to two ADMP421 digital MEMS microphones can be input to an ADAU1761 low power codec on a single PDM bit stream.
Circuit Description
| Product | Description |
| ADAU1761 | SigmaDSP® stereo, low power, 96 kHz, 24-bit audio codec with integrated phase-locked loop (PLL) |
| ADMP421 | Digital MEMS microphone |
The ADMP421 digital MEMS microphones are connected to the ADAU1761 with a PDM data signal, clock, power, and ground. The only necessary passive components in this circuit are a single 0.1 µF bypass capacitor for each ADMP421. Place the bypass capacitors as close to the VDD pin (Pin 4) of the ADMP421 as possible. A 100 Ω series resistor placed close to the BCLK/GPIO2 pin of the ADAU1761 may also be needed to properly drive the microphone clock signal and minimize ringing due to capacitive loading, depending on layout and trace length.
The ADMP421 power supply is provided from the MICBIAS pin of the ADAU1761. The MICBIAS pin can be set to either 0.9 × AVDD or 0.65 × AVDD, where allowable values of AVDD are between 1.8 V and 3.3 V
The two ADMP421 digital MEMS microphones in the circuit share a common time multiplexed data output line. Each microphone is set to provide output on either the left channel or the right channel in the output stream by tying the L/R SELECT pin to either the VDD pin (left) or the GND pin (right).
The ADAU1761 supplies the digital MEMS microphone clock from the BCLK/GPIO2 pin. The ADAU1761 must be a master on this clock line for proper operation. The ADMP421 can accept clock frequencies between 1 MHz and 3.3 MHz. By default, the clock output from the ADAU1761 is 64 × fS, but it can also be set to 32 × fS, 48 × fS, 128 × fS, and 256 × fS through the serial port control registers. With fS = 48 kHz, the default 64 × fS bit clock output is 3.072 MHz.
Register Settings
Three register bit fields must be set in the ADAU1761 to enable its digital microphone input. These setting are:
- JDFUNC[1:0] in Register R2 to 0b10—sets the JACKDET/ MICIN pin to digital microphone input mode
- MS in Register R15 to 0b1—sets the serial port to master mode
- INSEL in Register R19 to 0b1—enables the digital microphone inputs and disables the ADC inputs
Common Variations
This circuit can also be set up with an ADAU1361 instead of an ADAU1761. The primary difference between these two codecs is that the ADAU1761 has a SigmaDSP processor core and the ADAU1361 does not.
A mono microphone circuit using a single ADMP421 can be set up by removing one of the ADMP421 ICs and its associated bypass capacitor. The other connections remain the same in this mono configuration.
The ADMP521 is a higher signal-to-noise ratio (SNR) MEMS microphone and can replace the ADMP421 in this circuit. The ADMP521 has a 65 dB SNR, while the SNR for the ADMP421 is 61 dB. These two microphones are pin-compatible and footprint-compatible; therefore, no electrical connections need to be changed.
Learn More
The ADMP MEMS microphone products mentioned in this application note are manufactured by InvenSense, 1745 Technology Dr., San Jose, California 95110.