Voltage supervisors require a minimum supply voltage before generating a valid reset below the minimum supply voltage reset, following the supply voltage rail, generating the reset glitch. Reset glitch can trigger a false signal to the processor or critical load during power-up. This application note discusses the various aspects of a glitch-free supervisor.
A supervisor IC is a valuable addition to almost any system, as it increases reliability, improves system performance, avoids overvoltage transients, and prevents power failures. Semiconductor manufacturers are making a continuous effort to enhance the performance of voltage supervisor ICs. Power-on reset glitch is one of the performance areas the industry is trying to improve.
A supervisor IC requires a minimum voltage (VPOR) to generate a clean or reliable reset signal. At power-on, before the supply rail reaches VPOR, the state of the reset signal is undetermined. Generally, we call this a glitch on reset.
In this application note, we will discuss the fundamentals of reset glitch and learn how Maxim's approach overrules the traditional methods of glitch-free supervisors.
Topologies of Reset Driver
There are predominantly two different circuit topologies used for the RESET pin: open drain or push-pull. Both topologies use an NMOS pulldown MOSFET.
|Open-Drain Configuration||Push-Pull Configuration|
Open-drain outputs provide more flexibility to a system designer, as the output can be pulled up to any voltage rail in the system, which can be useful when they serve as inputs to a processor that might require a different voltage level (VIH, VIL). A push-pull output configuration is more useful in systems with similar voltage rails.
Power-On Reset Glitch
At power-up, the internal circuitry driving the output MOSFET is inactive until the rising supply voltage reaches VPOR. During this interval the output MOSFET remains off and Reset will rise in proportion to the pullup voltage (VPULLUP). Once the supply voltage is above VPOR, the internal MOSFET will drive the reset to a valid reset state. This unintended rise in Reset voltage as VCC rises from 0V to VPOR is commonly called reset glitch and can cause unreliable system operation.
Why a Glitch-Free Supervisor?
Generally, voltage supervisors control a Reset pin of a microcontroller or an Enable pin of a DC-DC controller. If the amplitude of reset glitch is near the minimum high logic threshold (VIH) of the microcontroller's Reset pin or the Enable of the DC-DC controller, it can trigger a false signal. Below are some critical applications where reset glitch is a key parameter for system design.
Interfacing with Low-Voltage Processor
Voltage supervisors can be used to monitor the low-voltage rails for FPGAs, ASICs, or DSPs where the voltage can be as low as 1V. In low-voltage processors, the I/O logic levels are very sensitive and VIH can be as low as 0.5V, as shown in Figure 3.
During power-up, FPGA, ASIC, or DSP devices need to be in the RESET state until all the supply rails are stable. Since RESET may have a glitch when VDD is below VPOR, this glitch can trigger an unknown state of those critical components. Once VDD is above VPOR, the internal MOSFET turns on, connects RESET to GND, and causes RESET to output the correct low logic level.
Controlling the Enable of a DC-DC Controller
In many applications, various DC-DC converters need a minimum supply voltage before they start, or they need enough energy at the input capacitor to support the inrush requirement of the converters. In the absence of sufficient energy, the inrush current may pull the input voltage down too low and cause the system or converter to reset. Controlling the Enable pin of the converter with the voltage supervisor holds the Enable pin low until the supply voltage becomes stable or above the monitoring threshold of the voltage supervisor.
During power-up, if the amplitude of the reset glitch is greater than the minimum enable high threshold voltage (VIH), the controller can be triggered and cause a system failure.
Discrete Solution of a Glitch-Free Operation
Currently, system engineers add an external circuit to a conventional supervisor to mimic the glitch-free feature of the supervisor as shown in Figure 6. By adding a standard JFET configured in a source-follower configuration, the voltage at the source will follow the voltage at VG (gate voltage) minus the threshold voltage of the JFET. The threshold of the JFET causes approximately a 1V drop between VG and VOUT and eliminates the voltage potential rise on the output until the internal circuitry becomes operational.
Integrated Solution for Glitch-Free Operation
Maxim Integrated has introduced the MAX16161/MAX16162 nanoPower, true glitch-free voltage supervisors. The MAX16161/MAX16162 can sink the current through the RESET pin even if VCC is 0V. This assures the valid state of RESET at a zero supply voltage and provides glitch-free power-up/-down operation (Figure 7).
The MAX16161/MAX16162 do not require any external component for glitch-free operation, delivering a tiny and cost-effective solution. The main feature and benefits of the MAX16161/MAX16162 are:
- No power-up glitch
- 825nA (typical) quiescent current for extended battery life
- Positive and negative level-triggered MR input options (MAX16161)
- MR debounce circuitry (MAX16161)
- Separate VCC and VIN inputs (MAX16162)
- Multiple available reset timeout periods
- Threshold voltage options: 1.7V to 4.85V (MAX16161); 0.6V to 4.85V (MAX16162)
- Tiny 4-bump WLP and 4-pin SOT23 packages
- Wide -40°C to +125°C operating temperature range
The MAX16161 is compared against a conventional supervisor with a power-on glitch to show how a glitch-free supervisor helps the LDO for smooth power-up. Figure 8 shows the basic connection of the LDO with a conventional supervisor, which is monitoring the IN rail (1.8V).
The threshold for the supervisor is set to 1.7V, which is above the minimum supply requirement of the LDO.
Figure 9 shows the power-up response of the LDO (MAX38908), where VBIAS (pink) is set to 3V, and IN (green) is rising from 0 to 1.8V. The voltage supervisor, with VPOR of 1.1V, monitors IN. RESET is connected to EN (blue) of the MAX38908 and is pulled to IN. The LDO output (yellow) falsely appears as Enable is above the VOH (1V) level. Once IN is above the VPOR (1.1V), RESET is pulled low since IN is less than the threshold voltage (1.7V). This discharges the output of the LDO.
After IN crosses the threshold voltage, the supervisor is pulled high and enables the LDO.
A similar test is repeated with the MAX16161 glitch-free voltage supervisor. In this experiment, we observe that RESET is pulled low even when IN is below VPOR and there is no false OUT at the LDO as shown in Figure 10.
A true glitch-free supervisor IC is no longer just a concept. With the nanoPower MAX16161/MAX16162, designers now have a supervisor IC that generates a reliable reset signal around zero supply voltage to enable power monitoring in low-voltage (< 1V) electronics, offered in a tiny package and consuming just 825nA of quiescent current to help extend system battery life.