How to Design a No-Opto Flyback Converter with Secondary-Side Synchronous Rectification


This application note explains the procedure for designing a no-opto flyback converter with secondary-side synchronous rectification using the MAX17690 and MAX17606 to achieve high efficiency and better thermal management.


Using a flyback converter for low- and medium-power applications is the preferred design choice due to the flyback converter’s simplicity and low cost. However, in isolated applications, the use of optocoupler or auxiliary winding for voltage feedback across the isolation boundary increases the number of components, and design complexity. The MAX17690, a no-opto flyback controller, eliminates the optocoupler or auxiliary winding, and achieves ±5% output voltage regulation over line, load, and temperature variations.

In low output voltage and high output current applications, the diode on the secondary side of the flyback converter dissipates a significant amount of power; this power loss reduces the converter’s efficiency. The MAX17606, a secondary-side synchronous MOSFET driver, helps in replacing the secondary diode with a MOSFET. This improves the efficiency and simplifies thermal management.

This application note provides the step-by-step procedure for designing the different components of the MAX17690 + MAX17606-based synchronous flyback design.

Design Example

The following specification is selected to demonstrate the design calculations for the MAX17690 and the MAX17606-based flyback converter. Figure 1 shows the typical application circuit for this application.

Application circuit
Figure 1. Application circuit.

Table 1. Design Specifications
Input voltage range 18V to 36V
Output voltage 5V
Maximum load current 1A
Steady-state output voltage ripple 1% of output voltage

Selection of Duty Cycle

Use the VINmin and VINmax from the selected specifications in the below equations to calculate the maximum duty cycle, Dmax.


VIN min is the minimum input voltage in volts.

VIN max is the maximum input voltage in volts.

Dmax is the maximum operating duty cycle. If the calculated duty cycle is > 0.65, then choose Dmax to be 0.65p.u.

Switching Frequency Selection

Use the below equations to calculate the maximum possible switching frequency, fsw.

For the present application, the switching frequency is selected as 150kHz. The RRT is calculated for the selected fSW.



A standard resistor of 33.2kΩ is selected.

Transformer Magnetizing Inductance and Turns Ratio

The MAX17690 and the MAX17606 are specifically designed for the isolated flyback converters operating in Discontinuous Conduction Mode (DCM) or Border Conduction Mode (BCM). Use the below equations to select the transformer magnetizing inductance (LMAG) for DCM operation.

For the present design LMAG is selected to be 46.4uH, and the allowable tolerance on the LMAG is ±10%. For the selected fsw and the LMAG, recalculate the Dmax using the equations below:


The MAX17606 programs the turn-off trip point and decides the instant at which the secondary MOSFET is turned off. Due to the variation on the turn-off point, the secondary MOSFET conduction time changes. To guarantee the DCM operation of the converter for the variations on the turn-off threshold, magnetizing inductance (±10%), and the switching frequency (±6%), select the turns-ratio (K) based on the below equations:


For the present design, K is chosen as 0.18 ±1%.

Selection of Current-Sense Resistor

For the selected LMAG and fSW, the primary peak current is calculated using the equation below:


The threshold voltage of the peak current-limit comparator is set at 100mV (typ) and 90mV (min). With the expected tolerance of ±10% on the LMAG and the ±6% on the fSW, to deliver the full-load power in all operating conditions, use the equations given below to calculate the current-sense resistor (RCS) value.

= 62.5mΩ

A standard resistor of 62.5mΩ ±1% is selected.

Selection of EN/UVLO and OVI Resistive Divider

The values of the resistor-divider can be selected so that the EN/UVLO pin voltage exceeds the 1.215V (typ) turn-on threshold at the desired input bus voltage (VSTART). The same resistor-divider can be modified with an additional resistor (ROVI) to implement input overvoltage(VOVI) protection in addition to the EN/UVLO functionality, as shown in Figure 1. When the voltage at the OVI pin exceeds 1.215V (typ), the device stops switching. With the preselected value of 10kΩ for ROVI:

For the present application VSTART and VOVI are selected to be 17.5V and 36.2V.

A standard resistor of 280kΩ is selected.

Selection of RTC Resistor

Since in this design the secondary MOSFET is always programmed to conduct at the sampling instant of the output voltage, there is no need to compensate the diode forward-voltage temp coefficient on the primary. For details on how to select the RTC resistor for the other applications, refer to the MAX17690 IC data sheet.

Selection of RIN, RFB, and RSET Resistor

The RIN, RFB, and the RSET resistors program the output voltage and sampling instant for proper sampling of the output voltage. Use the below equations to calculate these values:


Use the combination of standard resistors 274kΩ and 3.74kΩ to meet the required RFB value of 277.7kΩ.

= 166.6kΩ

A standard resistor of 165kΩ is selected for this application.
In practice, due to the drop across the secondary leakage inductance of the transformer, the measured output voltage can deviate from the target output voltage.  Use the below equations to readjust the output voltage to the desired value:

Soft-Start Capacitor Selection

For the desired soft-start time(tSS = 10ms), the SS capacitor is selected using:

= 50nF

The soft-start capacitor selected is 47nF for the present design.

Selection of RVCM Resistor

The resistor connected between the VCM pin and SGND is used to scale the common-mode voltage of internal circuits within the operating range. Follow the below steps to select the RVCM resistor value for proper operation.

  1. Calculate the internal scaling factor:

  2. = 111.1

  3. From the below table, choose the row that has the equal or higher value for Kc with respect to the calculated Kc in Step 1. Select the row with Kc = 160 for the present design.
  4. Kc RVCM (Ω)
    640 0
    320 75k
    160 124k
    80 220k
    40 Open
  5. Select the resistor value from the corresponding row as the RVCM (RVCM=124kΩ).

Primary MOSFET Selection

MOSFET selection criteria includes maximum drain voltage, primary peak/RMS current, the on-state resistance (RDS(ON)), total gate charge(QG), the parasitic capacitance(COSS), and the maximum allowable power dissipation of the package without exceeding the junction temperature limits. The voltage seen by the MOSFET drain is the sum of the input voltage, the reflected secondary voltage on the transformer primary, and the leakage inductance spike. The MOSFET’s absolute maximum VDS rating must be higher than the worst-case drain voltage.

The “RCD and RC Snubber Circuit” section covers the selection of snubber components to limit the drain-to-source voltage to VDSmax value selected in the above equation.

The RMS current in the MOSFET can be calculated using the below equation:

In the present application, the FDMS86252 part is selected as the primary MOSFET to achieve high efficiency. From the MOSFET data sheet RDS(ON) value , the conduction loss in the MOSFET can be calculated using the equation given below:

For the selected MOSFET, the equation below gives another loss component, switching loss.

From the MOSFET data sheet, the COSS at 100V is given as 60pF.


It is important to verify the maximum junction temperature of the MOSFET for the calculated losses using the below equation.

where TA is the ambient temperature, the RTH(JA) is the MOSFET thermal resistance from junction-to-ambient, and the PMOSFET is the total MOSFET losses.

In this high-efficiency design, for the selected MOSFET the total losses are a very small portion of output power, and its junction temperature is within the limits.

Use the below equation to calculate the IC driver losses for the selected MOSFET:

Secondary MOSFET Selection

The voltage seen by the MOSFET drain is the sum of the output voltage and the reflected input voltage on the transformer secondary. Make sure that the maximum secondary VDS voltage, when the primary MOSFET is turned ON is less than 60V. The MOSFET’s absolute maximum VDS rating must be higher than the worst-case drain voltage.

For the secondary MOSFET, the RMS current equation is given below:

For the stable operation of MAX17690 + MAX17606-based designs over the entire operating conditions, it is recommended to select the RDS(ON) of the secondary MOSFET such that the voltage across the MOSFET (at room temperature) is greater than the 100mV when the peak secondary current is flowing through the MOSFET.

In the present application, STL51N3LLH5 is selected as the secondary MOSFET.

The losses in the secondary MOSFET can be calculated using the loss equations provided in the primary MOSFET selection section and the maxim junction temperature can be verified to be within limits.

RCD and RC Snubber Circuit

Ideally, the primary external MOSFET experiences a drain-source voltage stress equal to the sum of the input voltage and reflected voltage across the primary winding during the OFF period of the MOSFET. In practice, parasitic inductors and capacitors in the circuit, such as leakage inductance of the flyback transformer, cause voltage overshoot and ringing in addition to the ideally expected voltage stress. Snubber circuits are used to limit the voltage overshoots to safe levels within the voltage rating of the external MOSFET. The typical RCD snubber circuit and the relevant waveforms are shown in Figure 2 and Figure 3.

Use the following equations to calculate the snubber components:


The voltage rating of the snubber diode is:

The RC component values are selected to be 60.4kΩ, 2.2nF.

Waveforms with RCD clamp
Figure 2. Waveforms with RCD clamp.

RC and RCD clamp circuitry
Figure 3. RC and RCD clamp circuitry.

The RCD clamp only limits the maximum voltage stress on the primary MOSFET, but the ringing due to interaction between Llk and Cpar on the drain node is not damped. Because the MAX17690 uses the drain voltage information to sample the output voltage, it is important to damp this ringing within 350ns from the NDRV falling. In designs where this ringing is dominant, an RC snubber placed across the transformer primary winding damps this ringing. Use the following steps for designing an effective RC snubber:

  1. Measure the ringing time period from the drain node voltage.

  2. Add a test capacitance starting with 100pF until the time period of the ringing is 1.5 to 2 x t1. For the added capacitance CD, measure the new ringing time period:

  3. Use the following equation to calculate the drain node capacitance:

  4. Use the following equation to calculate the leakage inductance:

  5. Now, use the following equations to calculate the RC snubber values:
  6. 1.5 to 2 x the

The Rc and Cc values are selected to be 47Ω and 220pF.

Selection of RTOFF Resistor

The MAX17606 IC data sheet explains the details of the RTOFF requirement and the selection. For a new design, assume the minimum blanking time required to be 1.5μs. The value of the RTOFF for the corresponding blanking time is 145kΩ. The standard resistor of 147kΩ can be selected for most of the designs to check the ringing time and to determine the actual value of RTOFF.
Based on the actual ringing time (tR) on the secondary MOSFET drain node shown in Figure 4, the new value of RTOFF can be selected using the equation below:

, where RTOFF is in kΩ and tR is in ns.

Secondary waveforms during synchronous MOSFET conduction

Figure 4. Secondary waveforms during synchronous MOSFET conduction.

Selection of RDRN Resistor

A resistor connected between drain node of the MOSFET and the DRN pin of the MAX17606 decides the secondary MOSFET turn-off instant. The below equation can be arrived using the equivalent circuit shown in Figure 5 depicting various parameters of the MOSFET and the MAX17606 associated components.


Lstray is the MOSFET package lead inductance (see Table 2 for lead inductance of various packages).

Vtrip: Vtrip should be selected as 0mV (corresponds to zero secondary current instant) for fsw = 100kHz and -6mV for fsw > 100kHz. This ensures the proper output voltage sampling and stable operation of the MAX17690 + MAX17606-based design.

Equivalent circuit of the MAX17606
Figure 5. Equivalent circuit of the MAX17606.

Table 2. Stray Inductance for Different MOSFET Packages

S.No Package Stray inductance (nH)
1 DFET 0.5


3 SO-8, PowerPAK® 1.8
4 DPAK 2.7
5 D2PAK 5.2

In practice, due to delay from the comparator circuit and MOSFET turn-off time (tOFF, given in the MOSFET data sheet), the RDRN equation given above does not predict the exact turn-off instant. The equation given below includes these delays and determines the turn-off instant:


, tDELAY can be calculated using Table 3.

Table 3. MAX17606 Turn-Off Delay

S.No (mV/μs) tDELAY(ns)
1 100.00 41
2 66.67 45
3 44.44 47
4 29.63 53
5 19.75 56
6 13.17 63
7 8.78 65
8 5.85 80

For the present design:


= 2.47kΩ

A standard resistor of 2.49kΩ is selected to be the DRN resistor.

Short Circuit Protection

The MAX17690 offers a hiccup scheme that protects and reduces power dissipation in the circuit under output short-circuit conditions. One occurrence of the runaway current limit, or output voltage less than 70% of regulated voltage, would trigger a hiccup mode that protects the converter by immediately suspending the switching for the period of 16,384 clock cycles. The threshold voltage of the runaway current limit comparator is set at 120mV (typ).

Minimum Load Requirement

The MAX17690 samples the output voltage feedback when the primary MOSFET is turned off and energy stored during the “ON time” is being delivered to the secondary. Therefore, it is mandatory to switch the external MOSFET to sample the reflected output voltage. Due to the default switching, a minimum amount energy is delivered to the output capacitor under no-load conditions. This small minimum load can easily be provided on the output by connecting a fixed resistor. In the absence of a minimum load, or a load less than the “minimum load,” the output voltage rises to higher values. To protect for this condition, a Zener diode of appropriate breakdown voltage rating can be installed on the output. Care should be taken to ensure that the Zener breakdown voltage is outside the output voltage envelope in both steady-state and transient conditions.

Under ideal circuit working conditions, the MAX17690 is designed to regulate the output voltage with 1% of full-load rated current on the output. With nonidealities, in most of the designs the current required to regulate the output voltage is less than 2% of the full-load rated current.

Note: Refer to the MAX17690 IC data sheet for more information.

Zener and the Series Resistor Selection

A Zener diode with a Zener breakdown of 10% to 15% higher than the output voltage can serve as a minimum load if preloading is not acceptable. For a 5V output voltage, the Zener breakdown (VZenerBR) is selected to be 5.6V. The maximum power dissipation in the Zener diode at no-load is calculated as:

where Iminload is the minimum load required.

In the present design, the 2% of full-load current is 20mA.

For the present design, a 5.6V, 0.5W MMSZ5232B Zener is selected. The resistor in series with the Zener is calculated based on the Zener breakdown voltage and the desired no-load output voltage.

For the present design, the output voltage at absolute no load is set at 6V.

A standard resistor of 22Ω is selected.

The power dissipation in this resistor is given by:

Input Capacitor Selection

For DC-DC applications, X7R ceramic capacitors are preferred due to their stability and a low effective series resistance (ESR) and effective series inductance (ESL) over temperature. The minimum value of the input capacitor is expressed as:

Considering a 2% ripple on the minimum supply voltage, the input capacitance is:


Two 2.2μF, 100V 1210 capacitors have been used in the present design considering the DC-biasing.

Output Capacitor Selection

The output capacitor is selected to limit the output voltage dip to 3% of output voltage for a 50% load step of the rated output current, using the equations below. The recommended bandwidth for the MAX17690-based converter is between fSW/20 and fSW/40. For the present design, the bandwidth is selected as 7kHz.

From the DC-bias characteristics, the 100μF, 6.3V 1210 capacitor offers 43mF at 5V. Hence, two 100μF, 6.3V 1210 capacitors are selected for the present design.

The output voltage ripple is determined by the bulk capacitance and ESR (RESR) of the output capacitor. When using ceramic capacitors, the ESR ripple can be neglected in most of the cases. For the high-ripple current aluminum capacitor, the capacitance calculation begins with the maximum acceptable ripple voltage and how this ripple should be divided between the ESR step and the ripple offered by the bulk capacitance.

For a 1% contribution to the total ripple voltage, the ESR of the output capacitor should be:

For a 1% contribution to the total ripple voltage, the bulk capacitance should be:

Loop Compensation

The loop compensation values are calculated as follows:

Load pole ==740.1Hz

Rz = 4.39kΩ

A standard resistor of 4.3kΩ is selected.

A standard capacitor of 47nF is selected.

== 493pF

A standard capacitor of 470pF is selected.

Note: When the ESR zero of the output capacitor is significant, the compensator pole capacitor (Cp) should be selected to cancel the ESR zero.

PCB Guidelines

Careful PCB layout is critical to achieve stable operation of any power-supply design. Follow the below guidelines for good PCB layout:

  1. Keep the loop area of paths carrying the pulsed currents as small as possible. In flyback design, the  loop created by the VIN bypass capacitor, transformer primary winding, MOSFET switch, and sense resistor is critical. Similarly, the high-frequency current path for the MOSFET gate switching from the INTVCC capacitor through the source of the MOSFET and sense resistor is also critical.
  2. The INTVCC bypass capacitor should be connected right across the INTVCC and PGND pins of the MAX17690.
  3. A bypass capacitor should be connected across the VIN and SGND pins and should be placed close to MAX17690.
  4. The IC’s exposed pad should be directly connected to the MAX17690’s SGND pin. The exposed pad should also be connected to the SGND plane in other layers by means of thermal vias under the exposed pad so that the heat flows to the large “signal ground” (SGND) plane.
  5. The RFB resistor trace length should be kept as small as possible.
  6. The PGND connection from the INTVCC capacitor and the SGND plane should be star connected at the negative terminal of the current-sense resistor.
  7. The proper sensing of drain-to-source voltage across the secondary MOSFET is critical in MAX17606. The RDRN should be Kelvin connected to the drain of the synchronous MOSFET. The source pin of the MOSFET should also be Kelvin connected to the MAX17606 GND pin.
  8. Connect the RTOFF resistor directly between TOFF pin and the MAX17606 GND pin. The return path should not be connected to ground plane.

Reference Design: MAX17690EVKITA#

MAX17690EVKITA# schematic
Figure 6. MAX17690EVKITA# schematic.

 Design & Simulate MAX17690 using EE-Sim