A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS

I. INTRODUCTION

Successive approximation register (SAR) ADCs have gained considerable research interest over the past decade or so [1]-[9]. The relatively simple architecture due to hardware reuse without requiring operational amplifiers (opamps) makes it more power efficient and easier to port between processes. Furthermore, the supply voltage scaling in advanced CMOS processes has less of a toll on SAR ADCs because the comparator only requires a small output swing to distinguish decisions from noise. This is unlike the opamps in pipelined ADCs or sigma-delta ADCs where reduced supply voltage translates to much lower opamp output swing due to fixed circuit overhead voltage drop, which leads to much decreased ADC signal to noise ratio (SNR).

One of the performance spaces that SAR ADCs excel at is high resolution at relatively low speed. They find many applications ranging from medical imaging, instrumentation, to industrial process control, etc. Compared to sigma-delta ADCs, which are also well suited in the low speed space, SAR ADCs distinguish themselves with the capability of converting one sample at a time, among others. Furthermore, SAR ADCs better handle multiplexed inputs compared to incremental sigma-delta ADCs especially when only lower oversampling ratio (OSR) is allowed, and SAR ADCs do not require much signal post-processing.

Typically, precision SAR ADCs [3], [4], which are generally defined at 16-bit and greater, sample at below a few MS/s. A few works [1], [2] have pushed the speed further. They use 2-bit/trial and the pipelined SAR architecture [7], [10] to speed up the operation, at the cost of added design complexity and a high accuracy amplifier. In addition, these ADCs typically have a sampling capacitance larger than 20 pF to achieve more than 90-dB SNR, which may require more power in the ADC driver than the ADC itself [11], [12]. Lastly, they employ off-chip linearity calibration [1]-[4] which takes significant test time and entails extra cost.

As system-on-a-chip (SoC) solutions are gaining more popularity in an effort to reduce overall system cost, as well as to improve system performance, the precision SAR ADCs aforementioned cannot meet the needs due to their large footprint, difficulty to drive, and high cost of testing. Furthermore, most of them are in older processes like 0.18 µm, which is not ideal for SoC chips due to their significant digital content. The work presented here describes a precision SAR ADC in 55-nm CMOS that addresses these issues, which was first reported in [13]. It is fast in the precision ADC category to enable more ADC output averaging where needed, which in turn allows one to have noisier individual conversions and thus dramatically smaller sampling capacitance. As an example, the user may average this ADC output 16 times to hit the 90-dB SNR target. This work also features a much smaller footprint as well as on-chip calibration which makes it well-suited for embedded applications.

This paper is organized as follows: In Section II, the architectural and block level designs are described. Circuit design techniques that help enable this ADC are presented in Section III, including optimal LSB repeats, one reservoir-capacitor per bit-capacitor DAC, calibration with existing LSB capacitors, and statistical residue measurement (SRM). Experimental results are shown in Section IV followed by the conclusion in Section V.

II. ARCHITECTURAL AND BLOCK LEVEL DESIGN

A. ADC Top Level

Fig. 1(a) shows the proposed ADC top-level block diagram.

It is a fully self-timed 16-bit asynchronous SAR ADC [14]-[17] with three MSBs resolved by the flash sub-ADC. The flash speeds up the conversion and attenuates the DAC output significantly to ease reliability concerns [17]-[19]. The ADC sampling network, which includes the 16-bit DAC and the 3-bit flash blocks other than the flash comparators, operates at 3.3 V to accommodate traditional precision applications, the rest of the circuits all operate under 1.2 V supply. The digital engine includes bit weight calibration and data reconstruction. The ADC operates in two modes, illustrated in Fig. 1(b). The default continuous mode has a periodic input convert clock. When the convert signal comes, the flash makes the MSB decisions and the result is fed to the DAC to start the bit trials. After the last bit trial finishes, the ADC enters the acquisition phase, when auto-zero is also performed on the comparator. This process is repeated when the next convert signal comes, at a known conversion rate. The other mode is the impulse mode, where the ADC converts on demand and goes to an inactive state afterwards while passively tracking the input signal. In this mode, after the convert signal goes active, the comparator is powered up and auto-zero is performed. The flash powers up the reference ladder and decides in parallel with the comparator auto-zero. It shuts down after the flash decisions are fed to the DAC. When all the subsequent bit trials finish, the ADC turns off and enters the passive acquisition phase until the next convert signal is detected. This impulse mode lets power scale with throughput when the input signal is sparse and the application does not require full speed conversion, such as many environmental or patient monitoring sensors. Though input bootstrapping circuit needs to be avoided in the impulse mode as the passive acquisition phase could last long and the bootstrapping capacitor may not hold its charge. To take advantage of the 55-nm deep sub-micron CMOS process, we designed the ADC to convert up to 16 MS/s, which is very fast in the precision ADC category but not so fast as to compromise the SAR ADC efficiency. The high speed operation gives the user an option to average the ADC output data further to lower noise. This in turn allows much noisier individual conversions and thus a much smaller sampling capacitance to dramatically reduce area. Compared to traditional precision ADCs that run slower and rely on accurate individual conversion, this ADC trades noise for speed to maintain the same efficiency but results in a much smaller footprint.

B. VDD Referenced Sampling

The impulse mode mentioned earlier requires passive acquisition, so that the ADC is not consuming any active power while it is tracking the input signal and waiting for the next convert signal to come. VDD referenced sampling technique is introduced to enable that. Fig. 2 shows the sampling circuit in acquisition phase while the comparator is turned off. In order not to consume any active power, we cannot use active circuitry to generate the common mode (CM) voltage V_CM shown in the figure. A conventional approach to solve this is to split each sampling capacitor C_sa into two halves, connect the top plate of one half to VDD and the other half to GND. After the acquisition, the top plates of the two halves are shorted together to realize the VDD/2 CM voltage. The downside of this approach is added layout routing complexity and the resulting parasitics. In addition, it also requires an extra clock phase to short the two top plates. In this design, we take advantage of the fact that the DAC output or comparator input swing is only 1/8th of ADC V_ref thanks to the flash sub-ADC that resolves the three MSBs. Assuming V_ref is 3.3 V and some reasonable amount of DAC output attenuation due to loading capacitors, we only have roughly ±150 mV max swing at each of the comparator inputs. This enables the use of the VDD supply, which is typically well regulated, to replace VCM at the top plate of the sampling DAC, thus avoiding an extra CM generator that would consume power. The upward of 150-mV transient at the comparator input may cause brief leakage through the top plate acquisition switch. To eliminate most of this potential leakage we may either use a high threshold core PMOS switch controlled by core supply, or use an IO NMOS switch controlled by IO supply. The latter has been implemented in this design. The slightly higher swing does not cause reliability concern to the input pair of the comparator, as will be covered in the comparator sub-section.

C. Flash Sub-ADC

The flash sub-ADC resolves three MSBs mainly as a tradeoff between added complexity and the amount of DAC output attenuation. In this design, shown in Fig. 3, a resistor ladder is used to generate the flash references, and the reference levels are dithered to match the SAR DAC dither, which is up to the equivalent of b12 weight. Dither is used here to improve ADC linearity [20]. The seven flash comparators sample the ADC input (up to 6.6V_pp,diff with V_ref = 3.3 V) and reference during acquisition phase Φ1 , and the comparison is done immediately afterwards in Φ₂, Φ₂’ is a slightly delayed version of Φ2. After the comparison is done in roughly 1.5 ns and the decisions are fed to the DAC, the comparator and resistor ladder is shutdown to preserve power. Since the SAR DAC has a built-in redundancy, the flash comparator offset and noise are not critical as long as the resulting decision errors are covered by the DAC redundancy. We allocate ¼ of the redundancy to tolerate the flash decision error. As such, the flash comparator is designed for speed and power to maximize its efficiency and minimize the overhead.

D. SAR Comparator

The comparator is a critical block in terms of power, noise, speed, and reconfigurability. Fig. 4 shows the block diagram of the comparator. The integrators before the latch are controlled by the programmable timer to trade integration speed with noise. The comparator reset signal comp_rst is boosted to ensure there is negligible memory effect in between two comparisons, even when the comparator input has a big step change. Fig. 5 shows the two integrator stage schematics and the latch stage. Cross-coupled positive feedback is used for both integrator loads to maximize DC gain and to eliminate the need for a common-mode feedback circuit. Both stages are auto-zeroed to minimize offset and 1/f noise for precision applications. The auto-zero phase shown in Fig. 5(d) overlaps with the ADC acquisition phase, both integrator stages store the offset information on the auto-zero capacitors C_az during this phase while the input to the integrators are differentially shorted. Two stages are used, instead of one, to achieve a wider range of integration gain versus time. The first integrator stage incorporates a folded cascode structure to enable the use of VDD as its input CM. Simulation shows that the input pair can handle up to VDD +400-mV transient input without stressing the transistor, as the source node of the input pair largely tracks the comparator input.

Comparator noise is the dominant source for the ADC conversion noise. We designed the steady state gain of the two integrator stages to be sufficiently high so that they operate in integration mode instead of linear settling mode to achieve better noise performance [21]. The gain of each integrator is given in the following equation.

Where gm is dominated by the input pair, C is the loading parasitic capacitors (not drawn) at op/om nodes in Fig. 5(a) and 5(b). The input referred noise power is inversely proportional to the gm of the input pair and integration time t, shown in (2). The γ factor accounts for the excessive noise from transistors other than the input pair.

Note that the auto-zero operation contributes to overall kT/C sampling noise, which is also accounted for in the design. The implemented comparator has an estimated noise of around 180 µV_rms.

E. DAC

The charge redistribution DAC with three capacitor array segments is shown in Fig. 6(a). Three segments are used to reduce the capacitance spread in each segment and to enable an 8-fF unit capacitor. The DAC sampling capacitance is only 1pF from b15-b12 and b12r, which greatly eases the input driver and reference buffer requirements. Three redundant capacitors (b12r, b8r, b4r) are included to tolerate decision errors [22], [23] from the flash sub-ADC and earlier bit trials. During the track phase, capacitors b11-b0 do not sample the input, but instead sample a random dither value to improve linearity. Up to 10 LSB repeats are included to improve noise performance, covered in more detail in Section III-A. Fig. 6(b) illustrates the operations of both sampling and non-sampling capacitors. One reservoir-capacitor per bit-capacitor DAC cell structure is employed to speed up operation and achieve signal independent bit weight errors. It is explained in depth in Section III-B.

For a SAR ADC, the earlier bit trials are less critical given that the comparator input is typically much larger than the conversion noise level. [24] and [25] take advantage of this by changing the comparator preamp loading capacitance to reduce power consumption for the earlier trials, without sacrificing the overall noise performance. In this design, we may optimize the bit trials further, with an example setting illustrated in Fig. 7. Given the redundancy employed at b8r and b4r, we divide the bit trials into several groups shown in the figure and set both smaller bit capacitor settling time and comparator integration time for earlier groups. The resulting settling error and higher comparator noise are tolerated by the redundant bits.

III. CIRCUIT DESIGN TECHNIQUES

A. Optimal LSB Repeats

The ADC noise comes from both the acquisition phase and the conversion phase, which is roughly 130 and 250 µV_rms, respectively, in this design. The acquisition phase noise is mainly kT/C sampling noise, which is a trade-off between noise level and area, as well as the power associated with driving the capacitance. Once the noise is sampled, it generally cannot be removed. Here we introduce a technique that focuses on reducing effective noise from the conversion phase only. The conversion noise affects the SAR comparator decision and it mainly originates from the comparator, the reference, and the series switch R_on and routing resistance at the comparator inputs. From (2) or [26], we know that it takes 4× power to reduce the comparator noise by 2×, assuming current efficiency gm/I remains the same. In [9], [27], and [28], comparator decision majority voting is used for critical bit trials where input to the comparator is very small to reduce conversion noise. This technique requires a detection circuit to identify the critical bit trials, which tends to be sensitive to process, voltage and temperature (PVT) variations. In [29], an adaptive-averaging technique was presented where b0 is repeated 8 times. It treats the first few LSB repeat bit trials as redundant trials to correct earlier DAC settling errors, and averages the rest of the repeat decisions after detecting a 01 or 10 transition during the LSB repeats. The effectiveness of this detection was limited due to the presence of conversion noise.

In this work, an optimal LSB repeat technique is proposed to reduce noise. The b0 decision can be repeated up to 10 times, depending on conversion rate and noise requirements. Unlike that in [29], we report that reconstructing the ADC output with the LSB repeat bits considered equivalent to the other bits yields better noise performance, i.e., the final ADC output is weighted sum of all the bits trialed, including the repeat bits. Fig. 8 illustrates the proposed LSB repeat technique using a 4-bit example. In the presence of conversion noise, b2 makes a wrong decision and the DAC output contains a residual error larger than one LSB after the regular b0 trial. With subsequent LSB repeats, the residual error will be pulled down because the mean conversion noise is zero. After a number of LSB repeats, the DAC output will start to move around the comparator threshold.

Furthermore, LSB repeats will not improve conversion noise, and the optimal number of LSB repeats can be determined given conversion noise level and the repeat bit weight. Fig. 9 shows simulation results of effective ADC noise versus number of repeats, at five different repeat bit weight settings. The ADC is ideal other than one LSB nominal conversion noise. We observe that depending on the conversion time available and thus the number of LSB repeats allowed, there exists an optimal repeat bit weight to get the minimal effective ADC noise. For example, if we have time to do four LSB repeats, choosing repeat bit weight b0/2 will yield better result than a b0 weight repeat. Also, as described earlier, for a given repeat bit weight, the effective ADC noise would stabilize after a number of repeats. In Fig. 9, the noise stabilizes at around five repeats for repeat bit weight b0. The smaller the repeat bit weight, the more repeats it takes for the effective ADC conversion noise to stabilize. As mentioned earlier, this design uses b0 repeat as it is found to be the most effective repeat bit weight given the designed noise level and speed.

The proposed LSB repeat technique essentially trades speed for noise, but the noise reduction more than makes up for the speed penalty in terms of efficiency or figure of merit (FoM). Fig. 10 shows the calculated FoM improvement of this design versus the number of repeats available, without accounting for the acquisition noise. Fig. 11 also compares measured results of this technique versus the adaptive averaging algorithm in [29]. The proposed approach improves noise further by up to 20%. In a more generic case, simulation results are given in Fig. 12 to compare the two LSB repeat algorithms. In this simulation, the ideal ADC has 1 LSB of conversion noise. Fig. 12(a) shows the effective ADC noise versus the number of LSB repeats, with 4 different repeat bit weights at 2×b0, b0, b0/2 and b0/4 respectively. Fig. 12(b) then aggregates the results from Fig. 12(a) and picks the lowest noise out of those four different repeat bit weights. For example, with five LSB repeats available for both techniques, minimum noise from adaptive-averaging is 0.6 LSB with b0 weight repeats, and minimum noise from the proposed is 0.52 LSB with b0/2 weight repeats. Fig. 12(b) demonstrates that the proposed optimal LSB repeat is again more effective by up to around 20%.

In addition, as no averaging is applied to the proposed optimal LSB repeats, the DAC output residue after the repeats could be processed to further reduce noise and quantization error. This will be covered in Section III-D.

B. One Reservoir-Capacitor per Bit-Capacitor DAC

DAC settling or reference settling during each bit trial is often a bottleneck for precision SAR ADC speed, especially when the reference is provided off-chip through chip bond-wires [30]. Another approach is to use an on-chip high speed reference buffer which comes at a cost of excessive power consumption. In [15] and [17], on chip reservoir capacitors are used as “references” to significantly improve DAC settling speed. Fig. 13 illustrates how using a reservoir capacitor improves DAC settling speed dramatically.

During the sampling phase, the reservoir capacitor Cr is charged up to the reference level. During the bit trial phase, the bit capacitors Cp and Cm absorbs the reference charge from Cr instead of an off-chip reference through the bond-wires. This makes the DAC settling much faster as the settling speed is only limited by the switch Ron and the bit capacitance. However, in both [15] and [17], the reservoir capacitors would need to be sufficiently big so that the reference inaccuracy due to charge sharing is minimized. To avoid this, in [17], DAC capacitors are separated from sampling capacitors to ensure charge drawn from the reservoir capacitor is signal independent. This leads to larger area and, more significantly, degrades noise performance. Reported in [13] and [3], we propose one reservoir-capacitor per bit-capacitor technique. This is in contrast to [15] where multiple reservoir capacitors are switched to one sampling capacitor; and [17] where one reservoir capacitor is shared with multiple bit capacitors. In this design, some of the bit capacitors (b15-b12, b12r) are also used as sampling capacitors. And unlike those in [15] and [17], each and every bit capacitor is driven to a reference during its bit trial by a unique pre-charged reservoir capacitor [see Fig. 6(b)] that is sized 10× that of the corresponding bit capacitors. It will be shown shortly that this DAC structure results in input-signal independent bit weights, enabling more straightforward calibration. As a result, relatively small reservoir capacitors are used, reducing area and easing pre-charging while maintaining the full speed benefit.

Fig. 14 illustrates at a conceptual level how this DAC structure achieves signal independent bit weights. Fig. 14(a) shows the simplified capacitor array during the first bit trial, where C_n-1 is the MSB capacitor and Cr_n-1 is the corresponding reservoir capacitor, C_n-2:0 are the rest of the bit capacitors in the DAC. Assuming the bit capacitor C_n-1 was either differentially shorted to V_CM (an option for sampling bit capacitors) or reset to common mode V_CM (for non-sampling bit capacitors) right before the bit trial, when the pre-charged reservoir capacitor Cr_n-1 connects to bit capacitor C_n-1, it is going to produce a DAC output step DAC_OP-DAC_OM independent of the input signal or the bit decision. The output step size is only a function of the capacitor ratios as the initial value on Cr_n-1 and the left hand side of C_n-1 are signal independent. Fig. 14(b) further illustrates the second bit trial, where the reservoir capacitor Cr_n-1 from the first bit trial is now part of the loading capacitors. This does not change the fact that DACOP-DACOM is still deterministic for the second bit trial, only the step size changes due to different loading capacitor values. The signal independent DAC output step size at each bit trial essentially represents the corresponding bit weight, so this one reservoir-capacitor per bit-capacitor DAC structure leads to signal independent bit weight errors from the charge sharing. An interesting observation is that even though the bit weight is signal independent, the charge drawn from each reservoir capacitor, illustrated in Fig. 14(b), is decision or signal dependent.

The conceptual explanation above assumes that the bit capacitor is shorted to a common mode right before the bit trial. In a more general case, the sampling bit capacitors may not have their bottom plates shorted before the bit trials, if there is a separate sub-ranging ADC that decides the first few MSBs. In this case, the bottom plates of the sampling capacitors could have initial value of V_in instead of a fixed V_CM right before the bit decision(s) are applied to the bit capacitor(s). We will prove mathematically that this still results in signal independent bit weights. Fig. 15(a) shows the MSB capacitor during the acquisition phase, Fig. 15(b) shows the MSB during its bit trial. DAC output loading capacitance are not shown in the figures. For simplicity, we start by assuming only the MSB acquires the reference from a reservoir capacitor, which may cause reference droop due to charge sharing. All of the lower bits have ideal references. Applying the charge conservation rule on node 1 and 2 right before the end of the acquisition phase and at the end of the conversion phase (where node 3 and 4 converge to V_CM as well), we can arrive at the following:

Where Vr_n-1 is the reference voltage drop on the reservoir capacitor Cr_n-1 after the charge sharing, V_ref is the ideal reference voltage, and bn-1 is the bit decision +1 or -1. We see that Vr_n-1 is proportional to input voltage V_in. The MSB weight at the end of the conversion is thus proportional to Vr_n-1 and thus V_in:

Where w_n-1,id is the ideal weight defined just by the MSB capacitor value. The aggregate ADC output D_out is defined by:

Where b_i is bit decision ±1, w_i is the corresponding half bit weight. Then we have D_out shown below as we assume all bit weights are ideal other than the MSB:

Plug (3) and (4) into (6), we get:

We can further define α_i and β_i as:

So we have:

And by definition:

Solving (10) and (11), we arrive at:

We see that D_out is effectively signal independent even though the MSB has signal dependent reference voltage droop shown in (3). And the effective MSB bit weight is not dependent on V_in, unlike w_n-1’ in (4). To generalize from the derivation above, let’s now assume each bit capacitor has its corresponding reservoir capacitor in the SAR DAC, we will arrive at the following general formula:

Effectively, the charge sharing from each reservoir capacitor contributes to the following constant and D_out can also be rewritten as:

The ideal bit weight defined by the capacitor value is scaled by a constant from reservoir capacitor charge sharing. And the effective half bit weight (w_i,id is defined as half bit weight) is shown below:

It is interesting to note that the bit weight w_i no longer corresponds to the DAC output step size at the bit trial. For example, DAC output step size for the MSB bit trial is linearly proportional to V_in as the bit capacitor has V_in as its initial value. (10) and (11) indicates that V_in dependent DAC output step would be further resolved by the lower bits, leading to (12) and (13) where the effective bit weights are signal independent. One caveat of this technique is, since the reference is not driven with an active circuitry during the bit trials, the input signal dependent nonlinear parasitic capacitance in the DAC will affect the charge sharing between the reservoir capacitor and the corresponding bit capacitor. This in practice limits the application of this technique to 18-bit ADC and below, assuming we are not using very large reservoir capacitors to save area. On the other hand, any fixed parasitic capacitors in the DAC capacitor array will not affect the signal independence of the bit weights, as they only modify the charge sharing ratios between the reservoir capacitors and the corresponding bit capacitors, resulting in slightly different but still signal independent bit weights.

C. Calibration with LSB Capacitors

To correct bit weight errors due to mismatches, parasitics, and reservoir-capacitor charge sharing errors, calibration is performed to help achieve 16-bit level linearity. A number of SAR ADC calibration approaches have been proposed in literature. In [31] and [32], equalization based digital engines are used to find the ADC bit weights. They require different ADC decision paths for the same input to make it work. In [33], the pipelined SAR ADC uses the back stage to calibrate the bit weights in the first stage. While in [34], an extra DAC is introduced to measure the bit weight errors in the main SAR DAC. Most recently, a calibration method using an extra trial is introduced [35], though it only works with analog bit weight compensation.

The on-chip foreground calibration with minimal overhead proposed here is similar in concept to [17] and [36]. However, we make it possible to calibrate the lower bits as well, which is essential for precision ADCs. The ADC measures the bit weights during calibration and compensates the errors in digital domain during normal operation. Instead of using the back stage or introducing an extra reference DAC to measure the bit weights, some of the LSBs in the ADC (b4r-b0 in this design) are used to calibrate the more significant bits (b4 and above), illustrated in Fig. 16. b4 is measured first with b4r-b0 using the existing SAR ADC feedback loop, while the ADC input is grounded and all the bits above b4 are not trialed. Specifically, we force b4 to 0 and get the ADC output codes which corresponds to the b4 weight at force 0, plus the ADC offset, and then we force b4 to 1 to get another set of output codes, the generalized formulas are shown below:

To remove the offset, we subtract the two to get:

After b4 is calibrated, then b5 is measured with b4-b0, and so on, as generalized in the following equation:

Multiple measurements are taken for each bit weight to average out the effects of noise. This calibration is made possible as redundancy (e.g., b4r) is available to increase the available range for measuring bit weight errors, shown in Fig. 17, otherwise the LSBs would not be able to measure the bit weight if it is larger than nominal weight. Also, as pointed out in [36] and illustrated in Fig. 18, ADC offset eats into the LSB measurement range. To achieve 16-bit level linearity, lower bits like b4 also need to be calibrated. Offsets in the system can be greater than the calibration range for these lower bits. To solve this issue, we introduce offset cancellation with fixed dither during the calibration. Fig. 6(a) illustrated that we have b11-b0 reused as dither capacitors. During the foreground calibration, we measure the ADC offset and cancel it by apply the appropriate amount of offset using the dither capacitors. Thus the ADC appears offset free during the bit weight calibration, enabling us to calibrate much smaller bit weights than those in [17] and [36], which is essential for achieving precision ADC performance.

D. Statistical Residue Measurement

As previously mentioned, after LSB repeats, the DAC output or comparator input still contains a small residual error V_res. The finite V_res is due to the conversion noise as well as the quantization error. As reported in [37]-[39], we may take advantage of the noisy comparator to measure the value of V_res and thus improve overall ADC accuracy. Fig. 19 illustrates how V_res measurement works. Assume the comparator has Gaussian noise, whose cumulative distribution function (CDF) is defined as:

Where we denote:

We can derive V_res as:

At the end of the regular trials or LSB repeats, the comparator makes a number of sequential decisions with its input unchanged. Based upon the probability of decision 1, the small comparator input can be estimated with (25) given knowledge of the comparator noise level. A small look up table (LUT) in the digital engine can be used to approximate the solution to this nonlinear (25) and the ADC digital output is compensated accordingly. Compared to those in [38] and [39], the number of comparator decisions in our work can be varied in silicon to demonstrate effectiveness and examine trade-offs with measured data.

This technique is only enabled when the ADC is running slower than 16 MS/s so that we have time left in the conversion phase after all the bit trials, allowing for the comparator to fire a number of times afterwards to estimate its input voltage, i.e., the DAC output residual voltage.

IV. EXPERIMENTAL RESULTS

The chip is fabricated in a 55-nm CMOS process. Die micrograph is shown in Fig. 20 and it measures 1.1 mm by 0.5 mm. The digital engine which also includes calibration is small thanks to the dense logic. The ADC input interface operates at 3.3 V while all other circuits use 1.2 V. By default, optimal LSB repeats is turned on and SRM is turned off to operate at 16 Msps. Fig. 21 shows the power breakdown where the DAC consumes 11.6 mW which also includes the estimated 2.8 mW from the level shifters. With the dramatically reduced sampling capacitance at 1.14 pF (including flash sampling capacitance) for precision ADCs, particular attention was paid to coupling through sub-fF level parasitics to maintain 16-bit linearity performance. Fig. 22 shows the DC linearity performance both with calibration OFF and ON. Before calibration, we see large INL error up to roughly 250 LSBpp mainly due to the charge sharing error from the reservoir capacitors. After calibration, the INL is -1.9/2.3 LSB. It is limited by sampling distortion because input bootstrapping was avoided to support passive sampling in impulse mode. Fig. 23 shows the spectrum with 100 kHz input signal, and the AC performance is summarized in Fig. 24, where SFDR/SNDR/SNR vs F_in and F_s are shown respectively. For most precision applications, input signal bandwidth is below 100 kHz, where over 97.5-dB SFDR is maintained. The SNR is over 78 dB and the equivalent ADC noise is about 3 LSB, meeting our design target. In Fig. 25, the measured ADC noise versus number of LSB repeats is shown to demonstrate its effectiveness. When operating at a lower frequency, statistical residue measurement (SRM) could be enabled to further improve accuracy. Fig. 26 shows the ADC noise versus number of SRM decisions. We observe that the ADC noise does approach the sampling noise level as number of SRM decisions increases. Note that for both noise plots, the conversion noise is configured higher to dominate the sampling noise to better observe the effect. The plot in Fig. 27 compares the linearity performance of this ADC with recent Nyquist ADCs from ISSCC and VLSI in the past 10 years with SFDR > 85 dB or SNDR > 80 dB [40]. Comparison with recently published medium speed and high resolution SAR ADCs is given in Table 1. [1] and [2] use a pipelined SAR architecture and are roughly 10× larger area with 20× larger input capacitance. In addition, all the other precision ADCs (16-bit+) rely on off-chip calibration and thus have much increased test cost.

V. CONCLUSION

A precision 16-bit SAR ADC that achieves 16 MS/s operation in 55-nm CMOS is presented in this paper. It supports both continuous mode and impulse mode operations. The fast conversion and small area is enabled by the small capacitor array and the signal independent, one reservoir-capacitor per bit-capacitor DAC structure. The minimal overhead on-chip calibration that calibrates down to lower bits helps ensure the ADC achieves 16-bit precision. Optimal LSB repeats and statistical residue measurement further improves the ADC accuracy and efficiency. Compared to traditional precision SAR ADCs, this ADC has 10× smaller area, 20× smaller sampling capacitance, and on-chip calibration to make it well-suited for precision SoC applications. To our knowledge, this work is also the first fast precision SAR ADC in a deep sub-micron CMOS node.

References

[1] C. P. Hurrell, C. Lyden, D. Laing, D. Hummerston, and M Vickery, “An 18 b 12.5 MHz ADC with 93 dB SNR,” IEEE J. Solid State Circuits, vol. 45, no. 12, pp. 2647-2654, Dec. 2010.

[2] A. Bannon, C. P. Hurrell, D. Hummerston, and C. Lyden, “An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2014, pp. 33-34.

[3] M. Maddox, B. Chen, M. Coln, R. Kapusta, J. Shen, and L. Fernando, “A 16 bit linear passive-charge-sharing SAR ADC in 55nm CMOS,” in IEEE Asian Solid-State Circuits Conf. (A-SSCC) Proc. Tech. Papers, Nov. 2016, pp. 153-156.

[4] D. Hummerston and P. Hurrell, “An 18-bit 2MS/s pipelined SAR ADC utilizing a sampling distortion cancellation circuit with -107dB THD at 100kHz,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2017, pp. 280-281.

[5] B. Ginsburg and A. P. Chandrakasan, “500 MS/s 5 bit ADC in 65-nm CMOS with split capacitor array DAC,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 739–747, Apr. 2007.

[6] N. Verma and A. P. Chandrakasan, “An ultra low energy 12-bit rate-resolution scalable SAR ADC for wireless sensor nodes,” IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1196–1205, Jun. 2007.

[7] S. Louwsma, A. J. M. v. Tuijl, M. Vertregt, and B. Nauta, “A1.35GS/s, 10b, 175mW time-interleaved AD converter in 0.13 μm CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 778–786, Apr. 2008.

[8] A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “A 0.5 V 1.1 MS/sec 6.3 fJ/ conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 4, pp. 1022–1030, Apr. 2012.

[9] P. Harpe, E. Cantatore, and A. van Roermund, “A 10b/12b 40 kS/s SAR ADC with data-driven noise reduction achieving up to 10.1b ENOB at 2.2 fJ/conversion-step,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3011–3018, Dec. 2013.

[10] C. C. Lee and M. P. Flynn, “A SAR-assisted two-stage pipeline ADC,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 859–869, Apr. 2011.

[11] R. K. Palani and R. Harjani, “High Linearity PVT Tolerant 100MS/S Rail-to-Rail ADC Driver with Built-in Sampler in 65nm CMOS,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2014, pp. 1-4.

[12] M. Kramer, E. Janssen, K. Doris, and B. Murmann, “A 14 b 35 MS/s SAR ADC achieving 75 dB SNDR and 99 dB SFDR with loop-embedded input buffer in 40nm CMOS,” IEEE J. Solid State Circuits, vol. 50, no. 12, pp. 2891-2900, Dec. 2015.

[13] J. Shen, A. Shikata, L. Fernando, N. Guthrie, B. Chen, M. Maddox, N. Mascarenhas, R. Kapusta, and M. Coln, “A 16-bit 16MS/s SAR ADC with on-chip calibration in 55nm CMOS,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2017, pp. 282-283.

[14] S.-W. M. Chen and R. Brodersen, “A 6 bit 600 MS/s 5.3 mW asynchronous ADC in 0.13μm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669–2680, Dec. 2006.

[15] J. Craninckx and G. Van der Plas, “A 65 fJ/conversion-step 0-to-50 MS/s 0-to-0.7 mW 9b charge-sharing SAR ADC in 90 nm digital CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2007, pp. 246–247.

[16] P. J. A. Harpe, C. Zhou, Y. Bi, N. P. van derMeijs, X.Wang, K. Philips, G. Dolmans, and H. de Groot, “A 26 uW 8 bit 10 MS/s asynchronous SAR ADC for low energy radios,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1585–1595, Jul. 2011.

[17] R. Kapusta, J. Shen, S. Decker, H. Li, E. Ibaragi, and H. Zhu, “A 14b, 80 MS/s SAR ADC with 73.6 dB SNDR in 65nm CMOS,” IEEE J. Solid State Circuits, vol. 48, no. 12, pp. 3059-3066, Dec. 2013.

[18] Y.-Z. Lin, C.-C. Liu, G.-Y. Huang, Y.-T. Shyu, and S.-J. Chang, “A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS,” in Proc. IEEE Symp. VLSI Circuits, Jun. 2010, pp. 243–244.

[19] S. Lee, A. P. Chandrakasan, and H. S. Lee, “A 1 GS/s 10b 18.9 mW time-interleaved SAR ADC with background timing skew calibration,” IEEE J. Solid-State Circuits, vol. 49, no. 12, pp. 2846–2856, Dec. 2014.

[20] M. Wagdy and M. Goff, “Linearizing average transfer characteristics of ideal ADC’s via analog and digital dither,” IEEE Trans. Instrum. Meas., vol. 43, p. 147, Apr. 1994.

[21] J. K. Fiorenza, T. Sepke, P. Holloway, C. G. Sodini, and H.-S. Lee, “Comparator-based switched-capacitor circuits for scaled CMOS technologies,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2658–2668, Dec. 2006.

[22] F. Kuttner, “A 1.2V 10b 20MSample/s non-binary successive approximation ADC in 0.18μm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2002, pp. 176–177.

[23] C.-C. Liu et al., “A 10b 100 MS/s 1.13 mW SAR ADC with binaryscaled error compensation,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2010, pp. 386–387.

[24] P. Harpe, Y. Zhang, G. Dolmans, K. Philips, and H. de Groot, “A 7-to-10 b 0-to-4 MS/s flexible SAR ADC with 6.5-to-16 fJ/conversion-step,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2012, pp. 472–473.

[25] W. Kim, H.-K. Hong, Y.-J. Roh, H.-W. Kang, S.-I. Hwang, D.-S. Jo, D.-J. Chang, M.-J. Seo, and S.-T. Ryu, “A 0.6 V 12 b 10 MS/s low-noise asynchronous SAR-assisted time-interleaved SAR (SATI-SAR) ADC,” IEEE J. Solid-State Circuits, vol. 51, no. 8, pp. 1826–1839, Aug. 2016.

[26] P. Nuzzo, F. De Bernardinis, P. Terreni, and G. Van der Plas, “Noise analysis of regenerative comparators for reconfigurable ADC architectures,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 6, pp. 1441–1454, Jul. 2008.

[27] M. Ahmadi and W. Namgoong, “A 3.3fJ/conversion-step 250kS/s 10b SAR ADC using optimized vote allocation,” in Proc. IEEE Custom Integr. Circuits Conf. (CICC), Sep. 2013, pp. 1–4.

[28] P. Harpe, E. Cantatore, and A. van Roermund, “An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2014, pp. 194–195.

[29] T. Miki, T. Morie, K. Matsukawa, Y. Bando, T. Okumoto, K. Obata, S. Sakiyama, and S. Dosho, “A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC with SNR and SFDR enhancement techniques,” IEEE J. Solid State Circuits, vol. 50, no. 6, pp. 1372-1381, Jun. 2015.

[30] G. Miller, M. Timko, H.-S. Lee, E. Nestler, M. Mueck, and P. Ferguson, “An 18b 10μs self-calibrating ADC,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 1990, pp. 168–169.

[31] J. A. McNeill, K. Y. Chan, M. C. W. Coln, C. L. David, and C. Brenneman, “All-digital background calibration of a successive approximation ADC using the split ADC architecture,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, no. 10, pp. 2355–2365, Oct. 2011.

[32] W. Liu, P. Huang, and Y. Chiu, “A 12-bit, 45-MS/s, 3-mW redundant successive approximation-register analog-to-digital converter with digital calibration,” IEEE J. Solid-State Circuits, vol. 46, no. 11, pp. 2661–2672, Nov. 2011.

[33] B. Verbruggen, K. Deguchi, B. Malki, and J. Craninckx, “A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2014, pp. 1-2.

[34] H. S. Lee, D. A. Hodges, and P. R. Gray, “A self-calibrating 15 bit CMOS A/D converter,” IEEE J. Solid-State Circuits, vol. 19, pp. 813–819, Dec. 1984.

[35] M. Ding, P. Harpe, Y.-H. Liu, B. Busze, K. Philips, and H. de Groot, “A 46 uW 13 b 6.4 MS/s SAR ADC with background mismatch and offset calibration,” IEEE J. Solid-State Circuits, vol. 52, no. 2, pp. 423–432, Feb. 2017.

[36] C. C. Lee, C.-Y. Lu, R. Narayanaswamy, and J. B. Rizk, “A 12b 70 MS/s SAR ADC with digital startup calibration in 14 nm CMOS,” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2015, pp. 62–63.

[37] J. Shen and R. Kapusta, “Accuracy enhancement techniques for ADCs.” U.S. Patent 9,071,261, issued June 30, 2015.

[38] B. Verbruggen, J. Tsouhlarakis, T. Yamamoto, M. Iriguchi, E. Martens, and J. Craninckx, “A 60 dB SNDR 35 MS/s SAR ADC with comparator-noise-based stochastic residue estimation,” IEEE J. Solid State Circuits, vol. 50, pp. 2002-2011, Sep. 2015.

[39] L. Chen, X. Tang, A Sanyal, Y. Yoon, J. Cong, and N. Sun, “A 0.7-V 0.6-μW 100-kS/s low-power SAR ADC with statistical estimation-based noise reduction,” IEEE J. Solid State Circuits, vol. 52, pp. 1388-1398, May 2017.

[40] B. Murmann, “ADC Performance Survey 1997-2016,” [Online]. Available: http://web.stanford.edu/~murmann/adcsurvey.html.

Acknowledgements

We thank A. Meenakshisubramanian, A. Bandyopadhyay, H. Ngo, D. McCartney, K. Nakamura and the entire layout, evaluation and support team.

Authors

Junhua Shen

(M’10) received the B.Eng. degree in information science and electronic engineering from Zhejiang University, Hangzhou, China, in 2002, and the M.Phil. degree in electronic engineering from The Chinese University of Hong Kong, Hong Kong, in 2004. He received the Ph.D. degree in electrical engineering from Columbia University, New York, NY, USA, in 2010. Since Feb. 2010, he has been with Analog Devices, Wilmington, MA, USA, as a design engineer and technical lead. His current research interests are in high performance ADCs and ultra-low power mixed-signal circuits. He holds 9 issued US patents. Dr. Shen was a co-recipient of the 2013 JSSC Best Paper Award.

Akira Shikata

received the B.S., M.S., and Ph.D degrees in electronics and electrical engineering from Keio University, Yokohama, Japan in 2008, 2010, 2013, respectively. From 2013 to 2015, he was a design engineer with Analog Devices Japan Design Center, Tokyo, Japan. Since 2015, he has been with Analog Devices, Wilmington, MA, USA, working on design of low power and precision data converters.

Lalinda D. Fernando

received the B.Eng. degree in electrical engineering from the University of Edinburgh, Scotland, UK, and the M.Eng. degree in electrical engineering from the University of Limerick, Republic of Ireland, in 2000 and 2004. Upon graduation in 2000, he joined Analog Devices, Inc. Ireland and thereafter Analog Devices, Inc. Wilmington, MA, USA, and has since been working on the design of monolithic high-resolution Nyquist converters and precision signal chain ASICs for medical imaging products used in electroanatomical mapping. He has authored and co-authored several technical papers in the domain of integrated circuit design and has received a number of U.S. patents.

Ned Guthrie

was born in New York in 1978. He received the B.A. and B.E. degrees in electrical engineering from Dartmouth College, Hanover, NH, USA, in 2001. In 2001, he joined Analog Devices, Wilmington, MA, USA, where he is currently a Digital Design Engineer. His current research interests include digitally assisted analog and low-power digital design.

Baozhen Chen

received the B.S. degree from University of Science and Technology of China, Hefei, China, in 2005, and the M.S. degree and Ph.D degree in electrical engineering from Iowa State University, Ames, Iowa in 2010. In summer 2009, he was an intern with BCD Semiconductor (now part of Diodes, Inc) in Shanghai, China. From 2010 to 2013, he was a design engineer with Maxim Integrated in North Carolina and California with audio group. From 2013 he was with Analog Devices, Inc at Wilmington, Massachusetts in Precision ADC group and Healthcare group. He is the author of seven articles and has received or has pending seven US patents. His research interest includes data converters, CMOS biosensors, and healthcare electronics.

Mark Maddox

received the B.S. degree in electrical engineering from the University of Toledo, in 1985 and the M.S. degree in electrical engineering from Cleveland State University, Cleveland, Ohio, in 1994. From 1988 to 1996, he was a design engineer with the Analog I/O group at Allen-Bradley now Rockwell International. Since 1996, he has been with Analog Devices, in Wilmington, Massachusetts working on the design of precision analog-to-digital converters. He is the author of 2 articles and has received or has pending 5 US patents. His research interest includes data converters and high accuracy analog circuits.

Nikhil Mascarenhas

was born in Mumbai, India in 1989. He received the B.E. degree in electronic engineering from University of Mumbai, India in 2011 and M.S in Computer Engineering from Arizona State University, US in 2014. He served as the chairperson for IEEE Student Chapter at Fr. Conceicao Rodrigues College of Engineering, Mumbai from 2010 to 2011. He currently works as an IC design Engineer at Analog Devices, Massachusetts. His research interests include Digital Signal Processing, Logic design for ADCs and mixed signal verification. When is not working he enjoys working out in the gym, playing tennis, soccer and ultimate Frisbee and reading.

Ron Kapusta

Ron Kapusta is an Analog Devices Fellow and holds the B.S. and M.Eng. degrees from the Massachusetts Institute of Technology. Upon graduating in 2002, he joined Analog Devices, designing data converters and sensor interface circuits for digital imaging systems. In 2014, Ron shifted focus to automotive technologies, working on electronics, photonics, and signal processing for LIDAR sensors. Ron has also been involved in program committees for several IEEE conferences.

Michael Coln

(M’80) received the B.S. degree from the California Institute of Technology, Pasadena, California, in 1976 and the M.S. and Ph.D. degrees in electrical engineering from the Massachusetts Institute of Technology, Cambridge, Massachusetts, in 1979 and 1985. He was with Hewlett-Packard Laboratories, Palo Alto, California from 1985 to 1988 as a Member of Technical Staff in the area of high performance converters. Since 1988, he has been with Analog Devices, Wilmington, Massachusetts, and currently is a designer in the Precision Converter group. His research and development interests include monolithic high-resolution Nyquist converters, high-accuracy analog integrated circuit design, and low-noise architectures for instrumentation. He has developed innovative monolithic architectures for extended signal chains, such as precision data acquisition ASICs for computed-tomography (CT) or digital X-ray medical imaging. More recently, he has been exploring approaches for high-resolution ADCs in nanometer technologies, including digital-intensive calibration and non-traditional architectures. He is the author or co-author of several technical papers in the area of integrated circuit design, and has received over three dozen U.S. patents. Dr. Coln was recognized as an Analog Devices Fellow in 2005. He was the co-recipient of the Lewis Winner Award for Outstanding Conference paper at ISSCC 2005, and the Jan van Vessem Best European Paper Award at ISSCC 2013.