### Abstract

Performance improvements in voltage regulators (VRs) are very important as specifications continue to be more and more challenging, especially in low voltage high current application areas such as data centers and especially artificial intelligence (AI). This article focuses on transinductor voltage regulator isolation and safety considerations for the motherboard.

### Introduction

While one possible performance improvement is to use coupled inductors,^{1–4} a similar approach was recently introduced as the transinductor voltage regulator (TLVR)^{.5–7} The schematic of a TLVR is derived from the model of a coupled inductor, but the physical behavior is different. In fact, a simple model of the coupled inductor is typically something that can be easily used in simulation to achieve correct waveforms, but it does not correspond to actual physics. TLVR, on the other hand, is pretty much built out of pieces as shown in the schematic, so the simulation model is closer to the physics of the real system in this case.

Since TLVR is a relatively new development, particular details and properties are still being studied. This article discusses the transient behavior of TLVR, which affects isolation requirements for the TLVR design itself.

### TLVR and Transient

The schematic of a TLVR, shown in Figure 1, is used in multiphase buck regulators.5 While the main inductor windings are still connected between switching nodes of the phases and V_{O}, the added auxiliary windings are electrically connected in series to each other and the tuning inductor, L_{C}. Removing L_{C} returns the circuit to just discrete (uncoupled) inductors in the buck converter. Shorting L_{C} out implies the strongest linking between the phases, as well as the fastest transient performance, but it also affects the current waveforms and the general amplitude of the current ripple. Practically, L_{C} is often chosen as a compromise between these two corner cases.

As in any multiphase buck converter, when a fast transient load step arrives, the change in output voltage causes the feedback to react, adjusting the voltage and current appropriately. A potential concern in a TLVR case is the fact that all auxiliary windings are connected in series, with a typical 1:1 transformer ratio to primary windings. The main TLVR windings have square waves applied to them at switching frequency, ideally phase-shifted in time between different phases. However, these phases are typically enabled to align during the transient to improve performance.

Consider an aggressive loading transient in a 12 V to 1.8 V application, where all high-side FETs in all phases turn on to ramp up inductor currents as fast as possible, so the (V_{IN} – V_{O}) = 10.2 V voltage is simultaneously applied to all main windings as shown in Figure 2. Actual waveforms will depend on the circuit parameters, but in the worst case, 1:1 transformers would generate 10.2 V on their secondaries so the resulting voltage pulse on the secondary side would be (V_{IN} – V_{O}) × N_{PH}. This is clearly a concern for safety. Figure 2 has realistic values for the TLVRs of 150 nH value, where the small leakage between the main and auxiliary windings is measured as 5 nH. A value of L_{C} = 160 nH is also shown. This L_{C} value is in a typical range for N_{PH}~6 but might be adjusted, especially for a different number of linked phases.

Figure 3 shows simulations for N_{PH }= 20 when all V_{X} switching nodes have a 100 ns pulse of 10.2 V: with L_{C} = 160 nH in Figure 3a, and L_{C} = open in Figure 3b. All secondary TLVR voltages are plotted to show how a series connection of the windings builds up the voltages. When the secondary windings of 20 linked phases are loaded with L_{C} = 160 nH, the voltages on the board reach ~123 V. But if L_{C} is disconnected, the voltage step can be as high as 197 V, as the secondary side is unloaded. The total voltage is closer to the worst case (V_{IN} – V_{O}) × N_{PH}.

However, the results in Figure 3 are still too optimistic. In reality, the simplified simulation in Figure 3 needs to add at least parasitics capacitances between the GND plane and fairly wide traces that connect secondary TLVR windings. A practical estimate for these parasitic capacitors is on the order of 5 pF. Adding 5 pF capacitors to each TLVR secondary node as shown in Figure 4 leads to the simulations shown in Figure 5. The added parasitic capacitors result in a lot of oscillations in the high Q circuit, as resistance is kept to a minimum for efficiency and transient considerations. The same N_{PH }= 20 case shows a voltage peak of 239 V when L_{C} = 160 nH is present, and 390 V, if L_{C} is broken off the board.

Notice that the value of the parasitic layout capacitors does not matter—it only affects the frequency and envelope of oscillations, but not the amplitude.

There seem to be at least two approaches to mitigate this high voltage issue. One is to make sure that phases cannot align during the transient, or at least no more than two to three phases. This could be considered for the controller
design, but it would clearly put a limit on how fast the transient response can be. Another approach is to limit the number of linked TLVR phases. But what are the practical limits of this approach, as N_{PH }needs to be high enough for current ripple to be contained, while N_{PH }also needs to be low enough to limit worst-case secondary voltage?

### Considerations for Linked N_{PH}

One derivation of current ripple in TLVR is shown.^{7} It is valid for any duty-cycle values, but since the equivalent circuit was simplified for the derivation (without dedicated leakage LK as a separate element in each TLVR); it is accurate for L_{C} = open, but then it starts accumulating an error that becomes infinite for L_{C} = short. It also assumes leakage in TLVR L_{K}<<L_{M}. Still, it provides a very reasonable estimate when L_{C} is not too small and L_{K} is not too big. Figure 6 compares normalized current ripple for a coupled inductor^{4} and for TLVR^{7} as a function of V_{O} (for V_{IN} = 12 V). In other words, starting with a discrete inductor L (red curve), different numbers of N_{PH }are either (a) magnetically coupled as a single coupled inductor or (b) electrically linked as TLVR. Particular conditions were set: TLVR = 150 nH, leakage 5 nH, L_{C} = 120 nH, and the coupling ratio L_{M}/L_{K} = 5 is assumed for the coupled inductor. Depending on N_{PH}, the magnetically coupled inductor significantly reduces current ripple from a discrete inductor with the same value L. The current ripple curves have notches or local minimums at D = V_{O}/V_{IN} = k/N_{PH}. Increasing L_{M} to infinity would make the current ripple equal to zero in these areas. The TLVR current ripple, on the other hand, is always larger than in a discrete inductor with the same value L. The TLVR current ripple also has notches at the D = k/N_{PH }areas, where the current ripple approaches the current ripple of the discrete inductor L. By increasing the number of linked phases, N_{PH }is clearly beneficial in decreasing the TLVR current ripple (Figure 6b).

Figure 7 shows current ripple as a function of linked TLVR phases for TLVR = 150 nH and different values of L_{C}. Lower L_{C} values introduce larger error, but the trends are very clear; lowering N_{PH }or decreasing L_{C} leads to an increase in current ripple. Notice that TLVR always has a larger ripple than a baseline discrete inductor (L_{C} = open). Assuming a big enough L_{C} value, it can be concluded that the minimum number of linked phases should be around N_{PH}_min~1/D, see Equation 1, to keep the current ripple impact under control. In other words, increase N_{PH }at least up to the first notch in the current ripple curve where duty cycles of different phases get close to overlapping.

Another conclusion is that the minimum desirable number of linked phases will increase with lower V_{O} as N_{PH}_min = V_{IN}/V_{O}. For V_{IN} = 12 V and V_{O} = 1.8 V, the TLVR solution roughly needs N_{PH}_min~6, while for V_{O} = 0.8 V, it would be N_{PH}_min~15, see Figure 8. Of course, a smaller number of N_{PH }is acceptable if there is extra impact on current ripple and therefore efficiency is tolerated. Notice that Figure 8 is plotted for the same TLVR = 150 nH and the same L_{C} values as in the V_{O} = 1.8 V case for consistency. This leads to smaller current ripple. But lowered V_{O} will make transient worse so it is very likely that the TLVR solution will be adjusted to improve transient, causing an increase in current ripple.

Assuming 12 V to 1.8 V applications, linking N_{PH }= 6 is targeted to keep the TLVR current ripple down. Figure 9 shows the worst-case secondary TLVR voltage when all phases on primary have a 100 ns pulse (V_{IN} – V_{O}). When L_{C} = 120 nH is present, the voltage on the secondary can reach 77 V. If L_{C} is broken off the PCB, the unloaded secondary voltage can oscillate up to 113 V.

A rough estimate for the worst-case secondary TLVR voltage would be as shown in Equation 2, where the 2× multiplier is coming from the oscillation instead of a pulse waveform.

TLVR internal leakage somewhat lowers this voltage peak, but that leakage is generally small by design. Correspondingly, the estimated V_{PEAK} would be 408 V for N_{PH }= 20 and 122 V for N_{PH }= 6, compared to the simulated 377 V (Figure 5b) and 113 V (Figure 8b), respectively. Then the estimated N_{PH}_max to keep the worst-case secondary voltage under the desired minimum V_{PEAK} could roughly be as shown in Equation 3. Assuming a 60 V maximum voltage rating on the PCB, a 12 V to 1.8 V application would have N_{PH}_max < 2.9 and for a 12 V to 0.8 V application, N_{PH}_max < 2.6. This creates a problem with keeping the current ripple contained, because N_{PH_}min = 6 and N_{PH}_min = 15 for V_{O} = 1.8 V and V_{O} = 0.8 V, respectively. If a safety rating requires a low enough voltage limit, then it seems that in practical applications, an extra current ripple increase would occur and therefore a more noticeable efficiency impact is expected.

Figure 10 shows N_{PH}_min (efficiency) and N_{PH}_max (safety) as a function of V_{O}, assuming a safety rating of V_{PEAK} = 60 V and V_{IN} = 12 V. A possible solution between N_{PH}_min and N_{PH}_max exists only above V_{O} = 3.5 V, then N_{PH}_max overrides it at lower voltages due to safety concerns, which leads to higher current ripple and related efficiency impact.

Of course, if N_{PH }is lowered, this also leads to an increase in the total number of added tuning inductors, L_{C}, since each linked group needs one.

### Conclusion

The TLVR approach is an improvement from a discrete inductor, but it mainly improves the transient while making a current ripple and therefore makes efficiency worse. To keep current ripple impact under control, linking N_{PH}_min > V_{IN}/V_{O} could be recommended. From the safety perspective, if the V_{PEAK} limit for the worst-case voltage on the PCB is desired, then linking no more than N_{PH}_max < V_{PEAK}/((V_{IN} – V_{O}) × 2) phases is needed. Safety standards would generally override the current ripple considerations, so a hit in current ripple impact and efficiency in the TLVR approach is to be expected.

The other possibility to mitigate high voltage concerns is to ensure that the controller never aligns more than some maximum number of phases, according to N_{PH}_max described earlier (two to three phases max for 60 V limit, etc.). The challenge with this approach is that it would limit how fast the system’s transient performance can be. Overlapping too many phases in steady-state operation should also be considered.