HFTA-06.0: Designing a Simple, Small, Wide-Band and Low-Power Equalizer for FR4 Copper Links

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Figure 1

   

Abstract

This discussion examines the design considerations, tradeoffs and a technique used to produce an equalization solution. The design technique suggests an alternative to developing complex models of the environment. Data are recorded from the target environment in the lab, replayed in the simulator, and altered by the circuit. Results from a working implementation are presented. This equalization approach is realized in a tiny chip-scale package that permits operating from 100Mbps to 6.4Gbps, uses less than 50mW, and is insensitive to coding.