Abstract

A compact power supply that provides a regulated 3.3V at currents up to 10A using the MAX5052A PWM controller is described here. This power supply operates from -36V to -72V and uses synchronous rectification to achieve efficiencies greater than 88% at 10A. It uses a single transistor forward converter with a reset winding and has a maximum duty cycle of 50%.It has input reverse voltage protection, and will regulate to zero load. The isolation voltage is 1500V and it has over-voltage and over-current protection. It can be turned on and off by the remote on/off pin and it has a thermal shutdown feature which protects the supply from excessive temperatures. The unit has hiccup current limit to limit the RMS current during an output short.

General Description

The output of this power supply is an isolated 3.3V/10A output, produced from an input is 36-72V DC. Airflow is required at higher ambient temperatures to get the full rated power.

The topology used is a single transistor forward, with a reset winding on the transformer to reset the core. The maximum duty cycle is less than 50%. The design uses the MAX5052A PWM controller.

Specifications for power supply

• Input -36V to -72V DC
• Output 3.3V
• Full load current 10A
• Minimum load 0A
• Load and Line Regulation ±1%
• Isolation voltage 1500 VDC
• Over-voltage protection
• Over-current protection
• Remote on/off (active high)
• Thermal shutdown
• Input reverse voltage protection
• Efficiency >85% at full load

Some of the features of the power supply are discussed below

The input of the power supply is protected from the application of reverse voltages by the circuit formed by Q6, R12, R13, R30 and D10. When the input voltage is of the correct polarity, then the body diode of Q6 is forward-biased. The zener voltage appearing across D10 fully turns on Q6 and the current now flows through the MOSFET Q6, thus limiting the dissipation. When the voltage is reversed, the MOSFET Q6 is turned off and most of the reverse voltage now appears across the MOSFET Q6 and very little current is drawn from the input.

Primary control, bias, drive and short circuit protection

The MAX5052A PWM controller has all the necessary control circuitry required for the design of an isolated power supply. The under-voltage lockout disables the drive until the voltage on the UVLO pin 1 goes higher than 1.23V. UVLO pin is enabled at 34V and is disabled on its way down at 32.6V. This guarantees that the power supply is on at 36V dc.

The feedback voltage from the opto-coupler appears on the junction of R14 and R15. Resistor R17, R16 and C14 form the compensation components on the primary. The current sense voltage appears on resistor R21. Resistor R20 and C15 filter out the current spike voltage at turn-on and the resultant voltage is fed to the CS pin on the MAX5052A controller. Since the duty cycle is less than 50% slope compensation is not required. Start-up of the converter is achieved through resistor R4 and C1.

Capacitor C1 charges up to 21.6V through R4 and when the UVLO pin is enabled, the PWM controller gate drive comes on. The digital soft start increases the pulse width slowly to the desired pulse width. The transformer winding voltage across pins 3 and 10 is rectified and the average rectified voltage will appear across C1. Inductor L1 is used for averaging purposes and must be sized such that the inductor is continuous at high line. This averaging circuit causes the power supply to go into hiccup mode during short circuit. Since the average output voltage on C1 is equal to the output voltage times the turns ratio of the primary bias winding to the secondary power winding, the voltage on C1 is proportional to the output voltage. Now when the output goes into current limit, the output voltage drops causing the primary bias voltage to drop. As the output goes deeper and deeper into current limit, the bias voltage will drop further until it drops below 9.74 volts, the bootstrap UVLO lower threshold. This will cause the power supply to shut down. The power supply will remain off until the bootstrap capacitor C1 charges up to 21.6V and the cycle will begin all over. This will limit the overall RMS short circuit current on the output. The drive voltage appears on the NDRV pin and this turns on and off the MOSFET Q3. The reset winding is formed by the primary windings from pins 12 to 1 and it has the same no of turns as the primary power winding from pins 2 to 11 on the transformer.

Secondary synchronous rectification and the output stage

The isolated secondary voltage appears across the secondary winding of the power transformer T1 between pins 5, 6 and pins 7 and 8. N channel MOSFET's Q1 and Q5 form the rectifying MOSFETS. Q1 is the forward stage MOSFET and Q5 is the freewheeling MOSFET. Q1 carries current when the transformer voltage on pins 7 and 8 is positive with respect to pins 5 and 6.

It is easy to derive the drive voltage for Q1 from pins 7 and 8. If the MOSFET Q1 where not turned on the body diode of Q1 would conduct when the primary FET Q3 is on. The voltage on pin 7 and 8 will vary from 9V to 18V when the input varies from 36 to 72V. This is sufficient to turn on Q1 and since the maximum Vgs rating on Q1 is 20V, we can apply the voltage on pins 7 and 8 directly on Q1 gate through resistor R1. This will turn on the MOSFET Q1 when the voltage on pins 7 is positive.

When the MOSFET Q3 is turned off, the voltage on pins 7 falls. This will turn off Q1 when the voltage drops below the threshold voltage of Q1. The diode D3 will speed up the turn-off of Q1. The gate drive waveform on Q5 is a little bit more difficult to obtain as compared to that of Q1. The gate of Q5 should be turned on after you turn off Q3 or Q1. It is also important that Q5 be turned off before turning on Q3 to avoid a short across the transformer secondary winding.

It is also important that Q5 be kept on during the portion of the interval where the secondary winding voltage is zero to maximize efficiency. This requires that the control signal of Q5 be obtained from the primary and sent across a separate isolation transformer T2.

T2 is a separate gate drive transformer that is used to obtain the drive signal for Q5. The voltage across the transformer secondary winding goes positive when the FET Q8 is turned on. Q8 is driven by the NDRV pin on U2. Since Q8 is a very small FET with a very low gate charge, the voltage across T2 secondary will go positive before the MOSFET Q3 is turned on which has a much higher gate charge than Q8 and a higher gate threshold voltage. This will cause a positive voltage to appear across the IN- pin of the MAX5048B SOT23 driver resulting in turning off MOSFET Q5.

We have thus achieved the turn-off of Q5 just before the turn-on of Q3. When Q3 is turned off by the NDRV pin In- pin on U1 goes low and turns on Q5. We have thus obtained the proper gate drive voltage waveform for Q5. A regulated bias voltage for U1 is obtained by the regulator formed by Q2,D6,R3 and C5. The voltage on C3 will vary from 9 to 18V while the voltage on C5 is regulated approximately at 9.5 volts. This voltage provides the appropriate gate drive voltage for Q5 and also lowers the dissipation in the gate charge turn-on and turn-off circuit for Q5. A 3A 30V schottky diode D4 is connected directly across the drain to source of Q5 so as to lower the reverse recovery in the body diode of Q5 by carrying the majority of the current when the MOSFET Q5 is turned off.

Inductor L2 and capacitors C7, C10 and C4 form the output low pass filter. The ESR of C7 is less than 5mΩ. The high frequency capacitor C9 returns all the high frequency currents caused by the primary to secondary winding capacitances back to the primary and lowers the noise appearing on the output due to these currents.

Secondary margining, regulation, OVP and primary remote on/off circuitry

U3 is MAX9001 a single comparator, an op-amp and a reference in a space-saving uMAX package. The 1.23V reference forms the reference for the voltage control loop. The industry standard trim function is achieved by the combination of the reference, R25, R27 and capacitor C17.

A resistor divider on the trim pin that is connected to R27 is used to trim the voltage up and down. When the trim pin is left open the output voltage will regulate at 3.3 volts. If the trim pin is shorted to RTN then the output voltage would try to regulate at 1.65 volts. This agrees with the industry standard trim settings. The LED current through the control optical coupler is controlled by the current through the resistor R24. The LED error current is given by

Id(s)=Vout(s)(1+sC16R22)/sC16R22R24.

Where Id is the LED error current and Vout is the error output voltage.

The comparator portion of U3 along with U4, R28, R29 and R26 form the OVP circuit on the secondary. The TL431 provides a 2.5V reference for the OVP sense circuit. The voltage divider R28 and R29 form the sense circuit of the output voltage for the OVP.

When the voltage on R29 exceeds 2.5 volts the optical coupler U6 turns on. This will cause the OUTB pin of the dual comparator U5 (MAX9053) to go high. D15 and R32 will cause it to be latched high and keep Q7 turned on and shut down the drive of Q3 causing the power supply to turn off.

The primary bias for the dual comparator and reference in U5 is obtained across C23. The resistors R34, R35 and the zener diode D16 provide a voltage of 3.8V for the Vcc pin in U5. This voltage is always present if the input voltage is applied to the input of the supply. Since the dual comparator draws very little current we can use two 42K resistors in parallel to provide the voltage for U5.

The remote on/off pin is connected to C18 and when it is left open, the remote on/off is in the on stage. The output of comparator A is high and the power supply is turned on as long the input voltage is above the under-voltage point and the power supply is not in OVP. When the remote on/off pin is brought below 2.5 volts, the output of the comparator A goes low. This will pull down on UVLO pin of U2 and cause it to turn off the supply. At the same time the OVP latch would be reset because the emitter of the OVP optical coupler U6 would be pulled low.

Thermal shutdown occurs if pin 5 on U8 goes low. U8 is a thermal sensor (MAX6501UKP105) with an open drain output pin on pin 5 that goes low when the temperature exceeds 105 degree C. Once the power supply shuts down due to thermal shutdown or OVP it has to be recycled by cycling input power or by cycling the remote on/off pin.

Turn on at -48V and full load

Channel 2 is the input voltage at 10V per division

Channel 1 is the output voltage at 0.5V per division

Turn on at -48V and no load

Channel 1 is the output voltage at 0.5V per division

Notice that there is no overshoot on turn-on at no load. This is due to the digital soft start function in the MAX5052A

Turn on at 72V with the input voltage reversed

Channel 1 is the input voltage at 20V per division

Channel 2 is the input current at 0.1A per division

The unit worked fine after the voltage was re-applied in the proper direction

Transient response from 7.5A to 5A to 7.5A (75% to 50% to 75% of rated load)

Channel 1 is the output voltage at 0.1V per division

Channel 2 is the output current at 2A per division

Test performed at 48V input

The overshoot for a 25% load increase is 80mv and the under-shoot for a 25% load decrease is 80mv. The recovery time is 100 microseconds.

Short circuit current at 72V input

Channel 1 is output short circuit current at 10A per division

The peak short circuit current at 72V is 30A. The RMS current is 10.8A The unit recovers to full rated load when the short is removed.

Peak to peak ripple noise at 20 Mhz bandwidth (36V input)

Channel 1 is 20 mv per division

The peak-to-peak ripple at 36V input and full load is 35.6 mv.

Peak-to-peak ripple at 48V input (20 Mhz bandwidth)

Channel 1 is 20 mv per division

The peak to peak ripple at 48V input and full rated load is 40.4mv.

Peak-to-peak ripple at 72V input (20 Mhz bandwidth)

Channel 1 is 20 mv per division

The peak to peak ripple at 72V input and full rated load is 46mv.

Note: The peak to peak ripple was measured with the standard measurement technique used for dc-dc modules. This involved the adding of a 1uF ceramic capacitor in parallel with a 10uf, 100 mΩ esr tantalum capacitor at the output and the noise was measured directly across the 1uF ceramic capacitor.

The ripple and noise will certainly improve in the production unit because the production unit would use 2oz copper. In the evaluation PCB we used 1oz copper on the board and this caused additional ESR on the output connections to the output capacitors. With the ESR reduced the ripple and noise would improve. Also in a new layout we would place the output capacitors (C7 and C20) directly across the output terminals.

Control loop measurements: Since the unit employs current mode control and uses synchronous rectifiers the output choke is always continuous. The measurement of the control loop revealed the crossover frequency to be 8.912 Khz and the phase margin to be 59 degrees.