MAXREFDES1020

The MAX15118 high-efficiency, current-mode step-down regulator with integrated power switches operates from 2.7V to 5.5V and delivers up to 18A output current in a small 2mm x 3mm package. The MAX15118 offers excellent efficiency with skip mode capability at light-load conditions, yet provides unmatched efficiency under heavy load conditions. The combination of small size and high efficiency makes this device suitable for both portable and nonportable applications.

The MAX15118 uses a current-mode control architecture with a high-gain transconductance error amplifier, which allows a simple compensation scheme and enables a cycle-by-cycle current limit with fast response to line and load transients. A factory-trimmed switching frequency of 1MHz (PWM operation) allows for a compact, all-ceramic capacitor design.

Integrated switches with low on-resistance ensure high efficiency at heavy loads while minimizing critical inductances.  

Other features include the following:

• ±1% Feedback Accuracy Over Load, Line, and Temperature
• Input Undervoltage Lockout
• Programmable Soft-Start
• Adjustable Soft-Start
• External Reference Input
• Selectable Skip Mode Option for Improved Efficiency at Light Loads

A current-mode synchronous buck is demonstrated using the MAX15118 for a 0.68V DC output application. The power supply delivers up to 6A at 0.68V. Table 1 shows an overview of the design specification.

This document describes the hardware shown in Figure 1. It provides a detailed systematic technical guide to designing a synchronous buck using Analog Devices' MAX15118 current-mode controller. The power supply has been built and tested, details of which follow later in this document.

Note: The MAXREFDES1020 uses the same board and PCB layout as the MAX15118 EV kit (MAX15118EVKIT).

Synchronous buck converters, as opposed to conventional buck converters, can achieve high efficiency in today’s low-voltage, high-current applications because they replace the catch diode of buck converters with a MOSFET. As a result, the power they dissipate in the off-period is reduced significantly.

In steady state, the low-side MOSFET is driven such that it is complementary with respect to the high-side MOSFET. This means whenever one of these switches is on, the other is off. In steady-state conditions, this cycle of turning the high-side and low-side MOSFETs on and off complementary to each other regulates V_OUT to its set value.

The basic operation of a synchronous buck converter can be explained from the simple circuit diagram shown in Figure 2. The main operation depends on the current in the inductor operated through main switch S1, generally a MOSFET, and the secondary switch S2. Initially when switch S1 is in the on state, the current starts flowing from the source through switch S1, inductor and to the load while the switch S2 is off. The operation time of switch S1 depends on the duty cycle. Now the current through the inductor charges the inductor. During this interval of time when the switch is in on state, switch S2 is in reverse bias and therefore switch S2 does not conduct.

For the next interval of time, when switch S1 is in the off state, the charged energy stored in the inductor now starts discharging. For this discharge of energy, the circuit needs to be closed. Now because the inductor is being discharged, the polarities of the inductor reverses and the switch S2 conducting state becomes forward-biased. When the duty cycle is very low, the inductor’s charging time is less when compared to the discharging time. Since switch S2 is in the on state during the discharging time, the secondary switch S2 conducts for a longer time than the main switch.

The synchronous rectifier switch is open when the main switch is closed, and the converse is also true. To prevent cross-conduction (both top and bottom switches are on simultaneously), the switching scheme must be break-before-make. Because of this, a diode is still required to conduct during the interval between the opening of the main switch and the closing of the synchronous-rectifier switch (dead time). When a MOSFET is used as a synchronous switch, the current normally flows in reverse (source to drain), and this allows the integrated body diode to conduct current during the dead time. When the synchronous rectifier switch closes, the current flows through the MOSFET channel. Because of the very low-channel resistance for power MOSFETs, the standard forward drop of the rectifying diode can be reduced to a few millivolts. Synchronous rectification can provide efficiencies well above 90%.

A feature offered in the MAX15118 is skip mode. Skip mode allows the regulator to skip cycles when they are not needed, greatly improving efficiency at light loads.

Skip mode offers improved light-load efficiencies but at the expense of noise, because the switching frequency is not fixed and is proportional to the load current.

Various waveforms for the synchronous buck topology are shown in Figure 3. During the first cycle when Q1 conducts, the input current gradually rises and flows through the inductor and capacitor. This results in the energy being stored in the inductor and the capacitor.

During the second cycle, Q1 turns off and, after some dead time, Q2 turns on. This results in the energy stored in the magnetic field of the inductor being released back into the circuit. As the energy stored in the inductor decreases, the capacitor starts discharging keeping the current flowing until the next cycle.

An important thing to note is that the MOSFETs Q1 and Q2 cannot be on at the same time as it would result in the input being connected to the ground. Hence, there should be some time interval between the on states of the MOSFETs. This time interval is called the dead time.

Design Procedure for Current-Mode Synchronous Buck

Now that the principle of the synchronous buck operation is understood, a practical design example can be illustrated. The design process can be divided into several stages: output voltage selection, inductor and capacitor selection, and setup of the compensation loop. This document is intended to complement the information contained in the MAX15118 IC data sheet.

The following design parameters are used throughout:

The above symbols are sometimes followed by parentheses to indicate whether minimum or maximum values of the parameters are intended, for example, minimum input voltage is indicated as V_IN(MIN). Unless otherwise noted, typical values are intended.

Step 1: Setting the Output Voltage

The MAX15118 output voltage is adjustable from 0.6V to 0.94V_IN by connecting FB to the center tap of the resistor-divider between the output and the GND. We choose the resistors R₁ and R₂ values so that the DC errors due to the FB input bias current do not affect the output voltage accuracy.

With lower value resistors, the DC error is reduced, but the power consumption increases.

Setting V_OUT = 0.68V and V_FB = 0.6V (typ), we get:

so select R₁ = 360Ω and R₂ = 2.7kΩ.

Step 2: Selecting the Inductor

A high-valued inductor results in reduced inductor-ripple current, leading to a reduced output-ripple voltage. However, a high-valued inductor results in either a larger physical size or a high series resistance (DCR) and a lower saturation current rating.

Typically, we choose an inductor value to produce a current ripple, ∆I_L, equal to 30% of load current giving an LIR of 0.3.

We select the inductor with the following equation:

where L = 0.5µH.

Additionally, we need to ensure that the following relationship is satisfied:

where:

Hence:

Step 3: Selecting the Input Capacitor

For a step-down converter, the input capacitor, C_IN, helps to keep the DC input voltage steady despite discontinuous input AC current. Use low-ESR capacitors to minimize the voltage ripple due to ESR.

We calculate C_IN using the following formulas:

Ensure that the input capacitor can accommodate the input-ripple current requirement imposed by the switching currents.

Step 4: Output Capacitor Selection

The key selection parameters for the output capacitor are capacitance, ESR, ESL, and voltage-rating requirements. These affect the overall stability, output-ripple voltage, and transient response of the DC-DC converter. The output ripple occurs due to variations in the charge stored in the output capacitor, the voltage drop due to the capacitor’s ESR, and the voltage drop due to the capacitor’s ESL.

Estimate the output-voltage ripple due to the output capacitance, ESR, and ESL as follows:

V_RIPPLE = V_RIPPLE(C) + V_RIPPLE(ESR) + V_RIPPLE(ESL)

where:

When using ceramic capacitors, which generally have low-ESR, ∆V_RIPPLE(C) dominates. When using electrolytic capacitors, ∆V_RIPPLE(ESR) dominates. Use ceramic capacitors for low ESR and low ESL at the switching frequency of the converter. The ripple voltage due to ESL is negligible when using ceramic capacitors.

Generally, a smaller inductor-ripple current results in less output-ripple voltage. Since inductor-ripple current depends on the inductor value and input voltage, the output-ripple voltage decreases.

When applying the load, limit the output undershooting by sizing C_OUT according to the following formula:

where ∆I_LOAD is the total load change, f_CO is the unity gain bandwidth (or zero-crossing frequency), and ∆V_OUT is the desired output undershooting.

We select C_OUT = 400µF. We obtain this value by putting four 100µF capacitors in parallel.

Step 5: Compensation

The MAX15118 uses a fixed-frequency, peak current-mode control scheme to provide easy compensation and fast transient response. The inductor peak current is monitored on a cycle-by-cycle basis and compared to the COMP voltage (output of the voltage error amplifier).

The regulator’s duty cycle is modulated based on the inductor’s peak current value. This cycle-by-cycle control of the inductor current emulates a controlled current source.

As a result, the inductor’s pole frequency is shifted beyond the gain bandwidth of the regulator.

System stability is provided with the addition of a simple series capacitor-resistor from COMP to GND. This pole-zero combination serves to tailor the desired response of the closed-loop system.

The peak current-mode controller’s modulator gain is attenuated by the equivalent divider ratio of the load resistance and the current-loop gain. G_MOD is the power modulator’s transconductance, and R_LOAD is the equivalent load resistance value.

K_S is the slope compensation factor calculated as:

where V_SLOPE = 130mV and g_MC = 150AV^-1.

Hence:

G_MOD becomes:

where:

hence, G_MOD =

G_MOD = 86.705

Select the desired crossover frequency. Choose f_CO equal to 1/10th of f_SW, or f_CO at 100kHz.

Select R_C using the transfer-loop’s fourth asymptote gain equal to unity, assuming f_CO > f_P1, f_P2, and f_Z1, R_C becomes:

g_M = 1.1mS, g_MC = 80AV^-1

and

V_SLOPE = 130mV

where:

K_S is the slope compensation factor calculated as:

Hence, R_C becomes:

= 1667Ω

R_C = 1.6kΩ. Selecting R₃ = R_C = 1.8kΩ.

Step 6: Selecting CC

C_C is determined by selecting the desired first system zero, f_Z1, based on the desired phase margin. Typically, setting f_Z1 below 1/5th of f_CO provides sufficient phase margin.

Selecting C₁₅ = C_C = 82nF.

Step 7: Setting the Soft-Start Time

The soft-start feature ramps up the output voltage slowly, reducing input inrush current during startup. The device utilizes an adjustable soft-start function to limit inrush current during startup. The soft-start time is adjusted by the value of C₁₆, the external capacitor from SS/REFIN to GND.

For a desired 6ms soft-start time, we calculate C₁₆ as:

The resistor, in series with the soft-start capacitor (R₁₄ or R_SS), improves load regulation. The recommended value for R_SS is approximately 330Ω. R_SS is needed to ensure that, during hiccup period, R_SS can be pulled down internally.

We select R₁₄ = R_SS = 470Ω.