MAXREFDES1010

Due to its simplicity and low cost, the flyback converter is the preferred choice for low-to-medium isolated DC-DC power-conversion applications. However, the use of an optocoupler or an auxiliary winding on the flyback transformer for voltage feedback across the isolation barrier increases the number of components and design complexity. The MAX17690 eliminates the need for an optocoupler or auxiliary transformer winding and achieves ±5% output voltage regulation over line, load, and temperature variations.

The MAX17690 implements an innovative algorithm to accurately determine the output voltage by sensing the reflected voltage across the primary winding during the flyback time interval. By sampling and regulating this reflected voltage when the secondary current is close to zero, the effects of secondary-side DC losses in the transformer winding, the PCB tracks, and the rectifying diode on output voltage regulation can be minimized.

The MAX17690 also compensates for the negative temperature coefficient of the rectifying diode.

Other features include the following:

• 4.5V to 60V Input Voltage Range
• Programmable Switching Frequency from 50kHz to 250kHz
• Programmable Input Enable/UVLO Feature
• Programmable Input Overvoltage Protection
• Adjustable Soft-Start
• 2A/4A Peak Source/Sink Gate Drive Capability
• Hiccup Mode Short-Circuit Protection
• Fast Cycle-by-Cycle Peak Current Limit
• Thermal Shutdown Protection
• Space-Saving, 16-Pin, 3mm x 3mm TQFN Package
• -40°C to +125°C Operating Temperature Range

An isolated no-opto flyback DC-DC converter using the MAX17690 is demonstrated for a 24V DC output application. The power supply delivers up to 300mA at 24V. Table 1 shows an overview of the design specification.

This document describes the hardware shown in Figure 1. It provides a detailed systematic technical guide to designing an isolated no-opto flyback DC-DC converter using Maxim’s MAX17690 controller. The power supply has been built and tested.

One of the drawbacks encountered in most isolated DC-DC converter topologies is that information relating to the output voltage on the isolated secondary side of the transformer must be communicated back to the primary side to maintain output voltage regulation. In a regular isolated flyback converter, this is normally achieved using an optocoupler feedback circuit or an additional auxiliary winding on the flyback transformer. Optocoupler feedback circuits reduce overall power-supply efficiency, and the extra components increase the cost and physical size of the power supply. In addition, optocoupler feedback circuits are difficult to design reliably due to their limited bandwidth, nonlinearity, high CTR variation, and aging effects. Feedback circuits employing auxiliary transformer windings also exhibit deficiencies. Using an extra winding adds to the flyback transformer’s complexity, physical size, and cost, while load regulation and dynamic response are often poor.

The MAX17690 is a peak current-mode controller designed specifically to eliminate the need for optocoupler or auxiliary transformer winding feedback in the traditional isolated flyback topology, therefore reducing size, cost, and design complexity. It derives information about the isolated output voltage by examining the voltage on the primary-side winding of the flyback transformer.

Other than this uniquely innovative method for regulating the output voltage, the no-opto isolated flyback converter using the MAX17690 follows the same general design process as a traditional flyback converter. To understand the operation and benefits of the no-opto flyback converter it is useful to review the schematic and typical waveforms of the traditional flyback converter (using the MAX17595), shown in Figure 2.

The simplified schematic in Figure 2 illustrates how information about the output voltage is obtained across the isolation barrier in traditional isolated flyback converters. The optocoupler feedback mechanism requires at least 10 components including an optocoupler and a shunt regulator, in addition to a primary-side bias voltage, VBIAS, to drive the photo-transistor. The error voltage FB2 connects to the FB pin of the flyback controller.

The transformer feedback method requires an additional winding on the primary side of the flyback transformer, a diode, a capacitor, and two resistors to generate a voltage proportional to the output voltage. This voltage is compared to an internal reference in a traditional flyback controller to generate the error voltage.

By including additional innovative features internally in the MAX17690 no-opto flyback controller, Maxim has enabled power-supply designers to eliminate the additional components, board area, complexity, and cost associated with both the optocoupler and transformer feedback methods. Figure 3 illustrates a simplified schematic and typical waveforms for an isolated no-opto flyback DC-DC converter using the MAX17690.

By comparing Figure 3 with Figure 2, it is evident that there is no difference in the voltage and current waveforms in the traditional and no-opto flyback topologies. The difference is in the control method used to maintain V_O at its target value over the required load, line, and temperature range. The MAX17690 achieves this with minimum components by forcing the voltage V_FLYBACK during the conduction period of DFR to be precisely the voltage required to maintain a constant V_O. When Q_P turns off, DFR conducts and the drain voltage of Q_P, rises to a voltage V_FLYBACK above V_IN. After initial ringing due to transformer leakage inductance and the junction capacitance of DFR and output capacitance of Q_P, the voltage V_FLYBACK is given by:

where:

V_FLYBACK is the Q_P drain voltage relative to primary ground
V_DFR(T) is the forward voltage drop of DFR, which has a negative temperature coefficient
I_LS(t) is the instantaneous secondary transformer current
R_S(T) is the total DC resistance of the secondary circuit, which has a positive temperature coefficient
n_SP is the secondary to primary turns ratio of the flyback transformer

The voltage of interest is (V_FLYBACK - V_IN) since this is a measure of V_O. An internal voltage to current amplifier generates a current proportional to (V_FLYBACK - V_IN). This current then flows through R_SET to generate a ground referenced voltage, V_SET, proportional to (V_FLYBACK - V_IN). This requires that:

Combining this equation with the previous equation for V_FLYBACK, we have:

We need to consider the effect of the temperature dependence of V_DFR and the time dependence of I_LS on the control system. If V_FLYBACK is sampled at a time when I_LS is very close to zero, then the term I_LS(t) x R_S(T) is negligible and can be assumed to be zero in the previous expression. This is the case when the flyback converter is operating in, or close to, discontinuous conduction mode. It is very important to sample the V_FLYBACK voltage before the secondary current reaches zero since there is a very large oscillation on V_FLYBACK due to the resonance between the primary magnetizing inductance of the flyback transformer and the output capacitance of Q_P as soon as the current reaches zero in the secondary, as shown in Figures 2 and 3. The time at which V_FLYBACK is sampled is set by resistor R_VCM.

The V_DFR term has a significant negative temperature coefficient that must be compensated to ensure acceptable output voltage regulation over the required temperature range. This is achieved by internally connecting a positive temperature coefficient current source to the V_SET pin. The current is set by resistor R_TC connected to ground. The simplest way to understand the temperature compensation mechanism is to think about what needs to happen in the control system when temperature increases. In an uncompensated system, as the temperature increases, V_DFR decreases due to its negative temperature coefficient. Since V_DFR decreases, V_O increases by the same amount, therefore V_FLYBACK remains unchanged. Since V_SET is proportional to V_FLYBACK, V_SET also remains unchanged. Since there is no change in V_SET there is no change in duty cycle demand to bring V_O back down to its target value. What needs to happen in the temperature compensated case is, when V_O increases due to the negative temperature coefficient of V_DFR, V_SET needs to increase by an amount just sufficient to bring V_O back to its target value. This is achieved by designing V_SET with a positive temperature coefficient. Expressed mathematically as:

where:
δV_DFR/δT is the diodes forward temperature coefficient
δV_TC/δT = 1.85mV/°C
V_TC = 0.55V is the voltage at the TC pin at +25°C.
Rearranging the above expression gives:

The effect of adding the positive temperature coefficient current, TC, to the current in R_FB is equivalent to adding a positive temperature coefficient voltage in series with V_DFR on the secondary side of value:

Substituting from the previous expression, this becomes:

We can now substitute this expression into the expression for V_O as follows:

and finally solve for RFB:

Values for R_SET, V_SET, and δV_TC/δT can be obtained from the MAX17690 data sheet as follows:

R_SET = 10kΩ
V_SET = 1V
δV_TC/δT = 1.85mV/°C

Values for V_DFR and δV_DFR/δT can be obtained from the output diode data sheet, and n_SP is calculated when the flyback transformer is designed.

The value of R_TC can then be calculated using the expression from earlier, restated below:

The calculated resistor values for R_FB and R_TC should always be verified experimentally and adjusted, if necessary, to achieve optimum performance over the required temperature range. Note that the reference design described in this document has only been verified at room temperature.

Finally, the internal temperature compensation circuitry requires a current proportional to V_IN. R_RIN should be chosen as approximately:

R_RIN = 0.6 x R_FB

Setting the V_FLYBACK Sampling Instant

The MAX17690 generates an internal voltage proportional to the on-time volt-second product. This enables the device to determine the correct sampling instant for VFLYBACK during the QP off-time. The RVCM resistor is used to scale this internal voltage to an acceptable internal voltage limit in the device. Selection of this resistor is described in detail in the MAX17690 data sheet.

Now that the principle difference between a traditional isolated flyback converter using optocoupler or auxiliary transformer winding feedback and the isolated no-opto flyback converter using the MAX17690 is understood, a practical design example can be illustrated. The converter design process can be divided into three parts: the power stage design, the setup of the MAX17690 no-opto flyback controller, and closing the control loop. This document is intended to complement the information contained in the MAX17690 data sheet.

The following design parameters are used throughout this document:

These symbols are sometimes followed by parentheses to indicate whether minimum or maximum values of the parameters are intended, for example, the symbol V_IN(MIN) is minimum input voltage. In addition, throughout the design procedure reference is made to the schematic.

Part I: Designing the Power Components

Step 1: Choose a Maximum Duty Cycle

The maximum duty cycle, d_MAX, occurs at maximum output power, P_O(MAX), and minimum input voltage, V_IN(MIN). The MAX17690 no-opto flyback controller uses peak current-mode control. Switching power converters using peak current-mode control exhibit subharmonic oscillations at duty cycles greater than 50% unless slope compensation is added to the sensed primary MOSFET current. Slope compensation is added internally in the MAX17690 to allow stable operation up to duty cycles of 66%, as specified in the data sheet. Choosing the maximum allowable duty cycle ensures the highest energy density for the power converter. For the current design, we have chosen:

d_MAX = 0.5  

Step 2: Calculate the Minimum Duty Cycle

The MAX17690 derives the current (ΔI_LP) in the primary magnetizing inductance by measuring the voltage (ΔV_RCS) across the current-sense resistor (R_CS) during the MOSFET on-time. So:

ΔI_LP is a maximum at d_MAX and V_IN(MIN) and is a minimum at d_MIN and V_IN(MAX) so:

and

Solving the two equations above, we have:

where ΔV_RCS(MIN) and ΔV_RCS(MAX) correspond to the minimum current limit threshold (20mV) and the maximum current limit threshold (100mV) of the MAX17690, respectively. So, for V_IN(MIN) = 19V, V_IN(MAX) = 40V, and d_MAX = 0.5, we have:

d_MIN ≈ 0.064  

Step 3: Calculate the Maximum Allowable Switching Frequency

The isolated no-opto flyback topology requires the primary side MOSFET to constantly maintain switching, otherwise there is no way to sense the reflected secondary-side voltage at the drain of the primary-side MOSFET. The MAX17690 achieves this by having a critical minimum on-time, t_ON(CRIT), for which it drives the MOSFET. At a given switching frequency t_ON(MIN) corresponds to dMIN. From the data sheet, the critical minimum on-time t_ON(CRIT) for the MOSFET drive output NDRV is 235ns. We can therefore calculate the maximum switching frequency as follows:

Since d_MIN is fixed by ΔV_RCS(MIN), ΔV_RCS(MAX), d_MAX, V_IN(MIN), and V_IN(MAX), we can choose a t_on(MIN), which is arbitrarily larger than t_ON(CRIT) to allow a reasonable design margin. So, if we choose t_ON(MIN) = 690ns we obtain a new switching frequency as follows:

Note that the MAX17690 should always be operated in the switching frequency range from 50kHz to 250kHz and t_ON(MIN) must be chosen accordingly to ensure that this constraint is met.

Step 4: Calculate Primary Magnetizing Inductance

Maximum input power is given by:

For the discontinuous flyback converter all the energy stored in the primary magnetizing inductance, L_P, during the MOSFET on-time is transferred to the output during the MOSFET off-time, i.e., the full power transfer occurs during one switching cycle. Therefore, because E = P x t, we have:

The maximum input energy must be stored in L_P during the on-time of the MOSFET, so:

We also know that the peak current in L_P, ΔI_LP(MAX) occurs at input voltage V_IN(MIN) and MOSFET on-time t_ON(MAX). So:

Rearranging this equation and squaring, we have:

and substituting:

we now have:

Finally, by rearranging we have an expression for the primary magnetizing inductance L_P:

If we estimate the power converter efficiency η_MAX = 0.85, then with V_IN(MIN) = 19V, d_MAX = 0.5, V_O = 24V, I_O(CL) = 0.36A, and f_SW = 106,000Hz, we have:

LP_(MAX) ≈ 41.7µH

This primary inductance represents the maximum primary inductance since it sets the current-limit threshold. Choosing a larger inductance will set the current-limit threshold at a lower value which would be undesirable. Assuming a ±10% tolerance for the primary inductance gives:

L_P ≈ 37.9μH 

Step 5: Calculate the Secondary to Primary Turns Ratio for the Flyback Transformer

Assume we are operating at the border between discontinuous and continuous conduction modes at V_IN(MIN) and P_O(MAX). Under this condition, the primary-side MOSFET is conducting for (d_MAX x τ_SW) and the secondary-side synchronous rectifier (or diode) is conducting for (1 - d_MAX) x τ_SW. Ideally, the primary volt-seconds per turn must balance with the secondary volt-seconds per turn; however, in practice, the primary to secondary coupling of the transformer is not perfect (giving rise to uncoupled leakage inductance) and both windings have series resistance. Effectively, this means that to obtain the required volt-seconds per turn on the secondary winding we need more volt-seconds per turn on the primary winding. We introduce a transformer efficiency factor, ηT, so that:

and

Assuming η_T = 0.9 and V_F = 0.5V, then with V_O = 24V, d_MAX = 0.5, and V_IN(MIN) = 19V, we have:

n_SP ≈ 1.4

Typical values of η_T range from 0.65 for an inefficient transformer design to 0.99 for a very efficient transformer design.

Step 6: Calculate the Peak and RMS Currents in the Primary Winding of the Flyback Transformer

The peak primary winding current occurs at V_IN(MIN) and d_MAX according to the following equation:

The RMS primary winding current can be calculated from ΔI_LP(MAX) and d_MAX as follows:

Step 7: Calculate the Peak and RMS Currents in the Secondary Winding of the Flyback Transformer

Again, assuming we are operating at the border between discontinuous and continuous conduction modes at V_IN(MIN) and P_O(MAX). The peak secondary winding current is related to I_O(MAX) and d_MAX as follows:

The RMS secondary winding current can be calculated from ΔI_LS(MAX) and d_MAX as follows:

Step 8: Summarize the Flyback Transformer Specification

We now have all the critical parameters of the flyback transformer:

Using the parameters in the table above, a suitable transformer can be designed.

Step 9: Calculate Design Parameters for Secondary-Side Rectifying Device

Depending on the output voltage and current, a choice can be made for the secondary-side rectifying device. Generally, for output voltages above 12V at low current (a few amps), a Schottky diode is used, and for voltages less than 12V, a synchronous switch is used. The current design is 24V/300mA output, so we outline a procedure for selecting a suitable Schottky diode for the secondary-side rectifying device.

Figure 4 shows a simplified schematic with the Schottky diode DFR.

The important parameters to consider for the Schottky diode are peak instantaneous current, RMS current, voltage stress, and power losses. Since DFR and LS are in series, they experience the same peak and RMS currents, so:

and:

When DFR is reversed-biased, V_IN reflected to the secondary-side of the flyback transformer plus V_O is applied across the drain source of Q_S, so:

V_DFR(REV) = n_SP x V_IN(MAX) + V_O
= 1.4 x 40V + 24V
≈ 80V

DFR has both V_IN losses due to its forward voltage and current and reverse bias losses. Allowing for a reasonable design margin, the ON Semiconductor part number MBRS4201T3G chosen for this design has the following specifications:

The power losses in the DFR can be approximated as follows:

P_TOT = P_FRWD + P_REV ≈ 515mW

where PFRWD is the loss due to IDFR(RMS) flowing through the forward-biased junction of DFR:

P_FRWD = V_DFR(FRWD) x I_DFR(RMS) ≈ 434mW

PREV is the loss due to the reverse-leakage current flowing through the reversed biased junction of DFR:

P_REV = V_DFR(REV) x I_DFR(REV) ≈ 81mW

Step 10: Calculate Design Parameters for Primary-Side MOSFET

The important parameters to consider for the primary-side MOSFET (Q_P) are peak instantaneous current, RMS current, voltage stress, and power losses. Because Q_P and L_P are in series they experience the same peak and RMS currents, so from Step 6:

I_QP(MAX) = I_LP(MAX) ≈ 2.17A

and

I_QP(RMS) = I_LP(RMS) ≈ 0.8A

When Q_P turns off, V_O reflected to the primary side of the flyback transformer plus V_IN(MAX) is applied across the drain-source of Q_P. In addition, until Q_S starts to conduct, there is no path for the leakage inductance energy to flow through. This causes the drain-source voltage of Q_P to rise even further. The factor of (1.5) in the equation below represents this additional voltage rise; however, this factor can be higher or lower depending on the transformer and PCB leakage inductances:

Allowing for reasonable design margin, the Vishay SiR872ADP was chosen for this design with the following specifications:

The power losses in the Q_P can be approximated as follows:

P_TOT = P_CON + P_CDS + P_SW ≈ 107mW

where:

P_CON is the loss due to I_QP(RMS) flowing through the drainsource on resistance of Q_P:

P_CON = I²_QP(RMS) x R_DS(ON) ≈ 28mW

P_CDS is the loss due to the energy in the drain-source output capacitance being dissipated in Q_P at turn-on:

And P_SW is the turn-on voltage-current transition loss that occurs as the drain-source voltage decreases and the drain current increases during the turn-on transition:

where IDRV is the maximum drive current capability of the NDRV output of the MAX17690 and I_QP(t-ON) is the instantaneous current in Q_P at turn-on. Since the flyback converter is operating in Discontinuous Conduction Mode, I_QP(t-ON) is zero and therefore P_SW is also zero.

Step 11: Select the RCD Snubber Components

Referring to Figure 5, when Q_P turns off, I_LP charges the output capacitance, C_OSS, of Q_P. When the voltage across C_OSS exceeds the input voltage plus the reflected secondary to primary voltage, the secondary-side diode (or synchronous switch) turns on. Since the diode (or synchronous switch) is now on, the energy stored in the primary magnetizing inductance is transferred to the secondary; however, the energy stored in the leakage inductance will continue to charge C_OSS since there is nowhere else for it to go. Since the voltage across C_OSS is the same as the voltage across Q_P, if the energy stored in the leakage inductance charges C_OSS to a voltage level greater than the maximum allowable drain-source voltage of Q_P, the MOSFET fails.

One way to avoid this situation arising is to add a suitable RCD snubber across the primary winding of the transformer. In Figure 5, the snubber is labeled R_SN, C_SN, and D_SN. In this situation, when QP turns off, the voltage at Node A is:

V_NODEA = V_CSN + V_IN

When the secondary-side diode (or synchronous switch) turns on, the voltage at Node B is:

So, the voltage across the leakage inductance is:

So:

The average power dissipated in the snubber network is:

Substituting Δt_SN into this expression we have:

The leakage inductance energy is dissipated in R_SN, so from:

We can calculate the required R_SN as follows:

Over one switching cycle we must have:

So, we can calculate the required C_SN as follows:

Generally, ΔV_CSN should be kept to approximately 10% to 30% of V_CSN. Figure 6 illustrates V_CSN, ΔI_SN, and Δt_SN. The voltage across the snubber capacitor, V_CSN, should be selected so that:

V_CSN < Q_P(DSMAX) – V_IN(MAX)

Choosing too large a value for V_CSN causes the voltage on the drain of Q_P to get too close its maximum allowable drain-source voltage, while choosing too small a value results in higher power losses in the snubber resistor. A reasonable value should result in a maximum drain voltage on Q_P that is approximately 75% of its maximum allowable value. The worst-case condition for the snubber circuit occurs at maximum output power when:

ΔI_SN = I_LP(MAX)

Assuming the leakage inductance is 3.5% of the primary inductance, then choosing V_CSN = 61V and ΔV_CSN = 1.5V, we get the following approximate values:

P_SN = 505mW
R_SN = 10kΩ
C_SN = 47nF

Finally, we consider the snubber diode, D_SN. This diode should have at least the same voltage rating as the MOSFET, Q_P. Although the average forward current is very low, it must have a peak repetitive current rating greater than I_LP(MAX).

Step 12: Calculate the Required Current-Sense Resistor

From Step 4 we have the maximum input power given by:

For the discontinuous flyback converter all the energy stored in the primary magnetizing inductance, L_P, during the MOSFET on-time is transferred to the output during the MOSFET off-time, i.e., the full power transfer occurs during one switching cycle. Therefore, since E = P x t, we have:

The maximum input energy must be stored in L_P during the on-time of the MOSFET, so:

Therefore:

and:

From Step 2 we have:

so:

Substituting values for ΔV_RCS, η, L_P, f_SW, V_O, and I_O(MAX) we have:

R_CS ≈ 51mΩ

where ΔV_RCS = 100mV, the maximum CS current-limit threshold of the MAX17690. We can choose a standard 50mΩ resistor for R_CS.

Step 13: Calculate and Select the Input Capacitors

Figure 7 shows a simplified schematic of the primary side of the flyback converter and the associated current waveforms. In steady-state operation, the converter draws a pulsed high-frequency current from the input capacitor, C_IN. This current leads to a high-frequency ripple voltage across the capacitor according to the following expression:

It is the ripple voltage arising from the amp second product through the input capacitor.

During the Q_P on-time interval from t₀ to t₁, the capacitor is supplying current to the primary inductance L_P of the flyback transformer and its voltage is decreasing. During the Q_P off-time time interval from t₁ to t₂, no current is flowing in L_P, and current is being supplied to capacitor from the input voltage source. According to the charge balance law, the decrease in capacitor voltage during time t₀ to t₁ must equal the increase in capacitor voltage during time t₁ to t₂. So:

And finally, since:

we have:

For maximum high-frequency ripple voltage requirement ΔV_CIN, we can now calculate the required minimum C_IN. An additional high-frequency ripple voltage occurs at the input due to the ESR of the input capacitor. This ripple voltage is generally much smaller than the amp second product voltage ripple and can be minimized by choosing a capacitor with low ESR.

There is high-frequency AC current flowing in C_IN, as shown in the center waveform of Figure 7. The selected capacitor must be specified to tolerate this maximum RMS current, I_CIN(RMS). From the simplified schematic:

I_LP = I_IN + I_CIN

Therefore:

where:

and from Step 6:

So:

The maximum RMS current in the input capacitor occurs at d_MAX, ΔI_LP(MAX), I_O(MAX), and V_IN(MIN).

I_CIN(RMS) ≈ 0.65A_RMS

An additional high-frequency ripple voltage is present due to the RMS current flowing through the ESR of the capacitor. Ceramic capacitors are generally used for limiting high-frequency ripple due to their high AC current capability and low ESR.

In addition to using a ceramic capacitor for high-frequency input ripple-voltage control as described above, an electrolytic capacitor is sometimes inserted at the input of a flyback converter to limit the input voltage deviation when there is a rapid output load change. A 100% load change gives rise to an input current transient of:

During this transient, there is a voltage drop across any series stray inductance, L_IN(STRAY), that exists between the input voltage source and the input capacitor of the power supply. So from:

we have:

We now have two values for C_IN. One for input high-frequency ripple-voltage control:

and a second for transient input voltage control:

If C_IN(ELE) > C_IN(CER), both ceramic and electrolytic capacitors must be used at the input of the power supply and ΔV_CIN should be limited to approximately 75mV to keep the AC current in the ESR of the electrolytic capacitor within acceptable limits. Otherwise, C_IN(ELE) is not required. In this case, the value of C_IN(CER) can be significantly reduced since there is no longer any requirement to limit ΔV_CIN to less than 75mV. Based on the current design specification, we have:

C_IN(CER) ≈ 31µ

and:

C_IN(ELE) ≈ 2.5µ

Since C_IN(ELE) < C_IN(CER), an electrolytic capacitor is not required. We can now recalculate C_IN(CER) based on a ΔV_CIN = 230mV:

C_IN(CER) ≈ 10µ

If we allow for a capacitor tolerance of ±10% and a further reduction of capacitance of 32% due to the DC bias effect (operating a 50V ceramic capacitor at 24V), our final nominal value is:

C_IN(CER) ≈ 16.7µ

We can almost achieve this by placing three 4.7µF ceramic capacitors (Murata GRM32ER71H475KA88) in parallel. The AC current in each capacitor is:

which is well within specification for the selected capacitor.

Step 14: Calculate and Select the Output Capacitor

High-frequency ripple voltage requirements are also used to determine the value of the output capacitor in a flyback converter.

Figure 8 shows a simplified schematic of the secondary side of the flyback converter and the associated current waveforms.

In steady-state operation, the load draws a DC current from the secondary side of the flyback converter. By examining the secondary current waveforms, we see that C_O is supplying the full output current I_O to the load during the time interval from t₂ to t₃. During this time interval, the voltage across C_O decreases. At time t₃, Q_P has just turned off and the secondary rectifying diode DFR (or the secondary synchronous switch Q_S) starts to conduct supplying current to the load and to C_O. The charging and discharging of C_O leads to a high-frequency ripple voltage at the output according to the following expression:

Again, as with the input capacitor, this is the ripple voltage arising from the amp second product through the output capacitor.

By the capacitor charge balance law, the decrease in capacitor voltage during time t₂ to t₃ must equal the increase in capacitor voltage during time t₁ to t₂. When the capacitor is discharging, we have:

Finally, since:

We have:

At maximum output current, the discontinuous flyback converter should ideally operates on the border between discontinuous and continuous conduction modes and so d_MAX should be substituted in the above equation.

For maximum high-frequency ripple voltage requirement ΔV_CO, we can now calculate the required minimum C_O.

C_O ≈ 5.2µF

As with the input capacitor, an additional high-frequency ripple voltage occurs at the output due to the output capacitor’s ESR and can be minimized by choosing a capacitor with low ESR.

Also, as with the input capacitor, there is high-frequency AC current flowing in C_O as shown in the center waveform of Figure 8. The selected capacitor must be specified to tolerate this maximum RMS current, I_CO(RMS). From the simplified schematic:

I_LS = I_O + I_CO

Therefore:

where:

I_O(RMS) = I_O 

and from Step 6:

so:

The maximum RMS current in the output capacitor occurs at d_MAX, ΔI_LS(MAX), I_O(MAX), V_IN(MIN), so:

I_CO(RMS) ≈ 0.43A_RMS

If we allow for a capacitor tolerance of ±10% and a further reduction of capacitance of 50% due to the DC bias effect (operating a 50V ceramic capacitor at 24V), our final nominal value is:

We can achieve this by placing four 4.7µF ceramic capacitors (Murata GRM32ER71H475KA88) in parallel. The AC current in each capacitor is:

which is well within specification for the selected capacitor.

Step 15: Summarize the Power Component Design

We have now made a first pass at calculating all the power components in the no-opto flyback converter using the MAX17690. Referring to the schematic, we have:

Part II: Setting Up the MAX17690 No-Opto Flyback Controller

Step 16: Setting Up the Switching Frequency

The MAX17690 can operate at switching frequencies between 50kHz and 250kHz (subject to the considerations in Step 3). A lower switching frequency optimizes the design for efficiency, whereas increasing the switching frequency allows for smaller inductive and capacitive components sizes and costs. A switching frequency of 106kHz was chosen in Step 3. R9 sets the switching frequency according to the following expression:

where R9 is in kΩ and f_SW is in Hz.

Step 17: Setting Up the Soft-Start Time

The capacitor C6 connected between the SS pin and SGND programs the soft-start time. A precision internal 5μA current source charges the soft-start capacitor C6. During the soft-start time, the voltage at the SS pin is used as a reference for the internal error amplifier during startup. The soft-start feature reduces inrush current during startup. Since the reference voltage for the internal error amplifier is ramping up linearly, so too is the output voltage during soft-start. The soft-start capacitor is chosen based on the required soft-start time (100ms) as follows:

C6 = 5 x t_SS ≈ 500nF

where C6 is in nF and t_SS is in ms. A standard 470nF capacitor was chosen.

Step 18: Setting Up the UVLO and OVI Resistors

A resistor-divider network of R1, R3, and R2 from VIN to SGND sets the input undervoltage lockout threshold and the output overvoltage inhibit threshold. The MAX17690 does not commence its startup operation until the voltage on the EN/UVLO pin (R3/R2 node) exceeds 1.215V (typical). When the voltage on the OVI pin (R1/R3 node) exceeds 1.215V (typical), the MAX17690 stops switching, thus inhibiting the output. Both pins have hysteresis built in to avoid unstable turn-on/turn-off at the UVLO/EN and OVI thresholds. After the device is enabled, if the voltage on the UVLO/EN pin drops below 1.1V (typical), the controller turns off; after the device is OVI inhibited, it turns back on when the voltage at the OVI pin drops below 1.1V (typical). Whenever the controller turns on, it goes through the soft-start sequence. For the current design R1 = 10kΩ, R2 = 316kΩ, and R3 = 12.7kΩ give rise to an UVLO/EN threshold of 18.1V and an OVI threshold of 41.2V

Step 19: Placing Decoupling Capacitors on V_IN and INTVCC

As previously discussed, the MAX17690 no-opto flyback controller compares the voltage V_FLYBACK to V_IN. This voltage difference is converted to a proportional current that flows in R5. The voltage across R5 is sampled and compared to an internal reference by the error amplifier. The output of the error amplifier is used to regulate the output voltage. The V_IN pin should be directly connected to the input voltage supply. For robust and accurate operation, a ceramic capacitor (C14 = 1µF) should be placed between V_IN and SGND as close as possible to the IC.

V_IN powers internal low dropout regulator of the MAX17690. The regulated output of the LDO is connected to the INTVCC pin. A ceramic capacitor (C4 = 2.2µF min) should be connected between the INTVCC and PGND pins for the stable operation over the full temperature range. Place this capacitor as close as possible to the IC.

Step 20: Setting Up the Feedback Components

R_SET, R_FB, R_RIN, R_VCM, and R_TC are all critically important to achieving optimum output voltage regulation across all specified line, load and temperature ranges.

R_SET resistor: This resistor value is optimized based on the IC’s internal voltage to current amplifier and should not be changed.

R5 = R_SET = 10kΩ

R_FB resistor: The feedback resistor is calculated according to the following equation:

Since we are using a synchronous MOSFET for rectification on the secondary side, we can assume that δV_DFR/ δT = 0, so:

From the MAX17690 data sheet, V_SET = 1V. The two resistors R4 = 160kΩ and R15 = 20kΩ form R_FB. Using one high value resistor and one low value resistor in series allows slight adjustment to the series resistance combination so that the output voltage can be fine-tuned to its required value, if necessary

R_RIN resistor: The internal temperature compensation circuitry requires a current proportional to V_IN. R_RIN is calculated according to the following equation:

R_RIN ≈ 0.6 x R_FB

R_VCM resistor: The MAX17690 generates an internal voltage proportional to the on-time volt-second product. This enables the device to determine the correct sampling instant for V_FLYBACK during the Q_P off-time. Resistor R6 is used to scale this internal voltage to an acceptable internal voltage limit in the device. To calculate the resistor, we must first calculate a scaling constant as follows:

where d_MAX = 0.5 and f_SW = 106,000. After K_C is calculated, the R6 value can be selected from the table below by choosing the resistance value that corresponds to the next largest K_C.

In the present case, R6 = 75kΩ.

R_TC resistor: The value of R_TC can then be calculated using the previous expression, restated below:

This completes the setup of the MAX17690 no-opto flyback controller.

Part III: Closing the Control Loop

Step 21: Determine the Required Bandwidth

The control loop’s bandwidth determines how quickly the converter can respond to changes at its input and output. If we have a step change in output current, the voltage across the output capacitor decreases as shown in Figure 9.

The control loop detects this reduction in output voltage and increases the duty cycle of Q_P to supply more current to the output capacitor. The amount of time required by the control loop to increase the duty cycle from its minimum value to its maximum value is the response time, τ_RES, of the control loop. For the MAX17690 we have:

where f_C is the bandwidth of the power converter. If we apply a switching load step of amplitude ΔI_STEP at a frequency of (1/τ_RES) and a 50% duty cycle, then, to limit the output voltage deviation to ±ΔV_O(STEP), we must have a minimum output capacitance of:

Combining the two previous equations, we have:

It is normal to specify ΔV_O(STEP) for a load step from 50% to 100% of the maximum output current. We have already calculated C_O(MIN) = 11.5µF in Step 13, f_SW = 106,000Hz, so based on a 3% maximum ΔV_O(STEP):

f_C ≈ 3.3kHz

Step 22: Calculate the Loop Compensation

The MAX17690 uses peak current-mode control and an internal transconductance error amplifier to compensate the control loop. The control loop is modeled, as shown in Figure 10, by a power modulator transfer function G_MOD(s) an output-voltage feedback transfer function G_FB(s) and an error amplifier transfer function G_EA(s).

The power modulator has a pole located at f_p(MOD) determined by the impedance of the output capacitor C_O and the load impedance R_L. It also has a zero at f_z(MOD) determined by the impedance of C_O and the ESR of C_O. The DC gain of the power modulator is determined by the peak primary current ΔI_LP and the current-sense resistor R_CS. So:

and:

The output voltage feedback transfer function G_FB(S) is independent of frequency and has a DC gain determined by V_IN, V_FLYBACK, and V_sSET as follows:

The transconductance error amplifier of the MAX17690 should be set up in a configuration to compensate for the pole at f_p(MOD) and the zero at f_z(MOD) of the modulator. This can be achieved by Type II transconductance error amplifier compensation shown in Figure 11.

This type of compensation scheme has a low frequency pole at f_p-lf(EA) due to the very large output resistance R_O (30mΩ - 50MΩ) of the operational transconductance amplifier (OTA). It has a zero at f_Z(EA) determined by C_Z and R_Z of the compensation network, and it has an additional pole at f_P(EA) determined by C_P and R_Z of the compensation network. So:

and:

To achieve stable operation, we must ensure that:

Set the closed loop gain at f_C equal to 1:

Place the zero in the error amplifier network at the same frequency as the pole in the power modulator transfer function:

The frequency f_z(MOD) at which the zero occurs in the power modulator transfer function depends on the ESR of C_O. If ceramic capacitors are used for C_O, f_Z(MOD) will generally be much higher than f_C. However, if the ESR of C_O is large, f_Z(MOD) could be lower than f_C. This is a very important point since both the gain of the power modulator at f_C, and the gain of the error amplifier at f_C depend on whether f_Z(MOD) is greater than or less than f_C. This is illustrated in Figure 12.

By examining the gain plots in Figure 12, we see that for f_Z(MOD) > f_C:

and for f_Z(MOD) < f_C:

For the current design, we have:

and:

where C_O = 11.5μF as calculated in Step 13 and ESR_CO = 1mΩ for four Murata GRM32ER71H475KA88 capacitors in parallel.

Since f_Z(MOD) > fC:

and since G_FB is independent of frequency, we have:

We can now set the closed-loop gain equal to 1 as follows:

Rearranging we can calculate:

Substituting ΔI_LP from Step 12:

Finally, we can calculate the remaining components, C_Z and C_P, in the error amplifier compensation network as follows:

and: