Hardware Requirements for Lowest Power Consumption in Power-Down Mode for the MAXQ1065

Introduction

Setting the PWDN pin of the MAXQ1065 Cryptographic Controller device to GND puts it into the power-down mode. The basic setup shown in the MAXQ1065 data sheet however does not achieve the lowest possible power consumption in power-down mode. To achieve this, there are some specific hardware requirements. This application note discusses the hardware requirements for the MAXQ1065 to put it into the ultra-low power consumption power-down mode. The application note first shows the block diagram and then lists the extra components needed for this specific mode.

MAXQ1065 Ultra-Low Power Block Diagram

Figure 1 shows the block diagram that can be used to achieve the lowest possible power consumption using the MAXQ1065 power-down mode. At both 1.8V/3.3V V_DD this setup reduces the current consumption by approximately 75%. Four pullup and four pulldown resistors are all that is needed to get the MAXQ1065 into this ultra-low power consumption power-down mode.

MAXQ1065 Ultra-Low Power Component List

Table 1 lists the details of the components shown in Figure 1.

Summary

This application note has covered the additional hardware needed to put the MAXQ1065 Cryptographic Controller into its ultra-low power consumption power-down mode. For more details on the regular operation of the MAXQ1065 power-down mode, refer to the MAXQ1065 device data sheet.