DS33R41 Multichip-Module BSDL Testing

Introduction

When manufacturing hardware for a telecommunications system, one of the basic tasks is to test the system for any production flaws. While there are many ways to test the hardware, one of the most popular methods uses the Joint Test Action Group (JTAG) boundary-scan method. The boundary-scan test method involves some minor changes to the hardware before production so that hardware verification can be performed after production. During design, all of the Integrated Circuit (IC) devices which support JTAG are connected in a serial daisy-chain fashion through the JTAG test access port. Verification is done by a specialized JTAG test system which connects to the test access port. The JTAG test system then uses a combination of the printed wiring board (PWB) netlist, Boundary-Scan Description Language (BSDL) files, and PWB connectivity test vectors to verify the pin-to-pin connections.

BSDL testing is straightforward. Nonetheless, multichip module devices like the DS33R41 Inverse-Multiplexing Ethernet Mapper with Integrated Quad Port T1/E1/J1 Transceiver cannot be properly described by a single BSDL file because there are multiple die in a single package. This shortcoming can be overcome with simple modification to the PWB netlist and by using two BSDL files to describe the device package instead of just one.

Modifying the Printed Wiring Board Netlist

Before JTAG boundary scan testing can be performed, the portion of the PWB netlist that describes the external connections to the DS33R41 package must be modified to split those connections between the internal DS33Z41 die and DS21458 die. Once completed, the netlist will define the DS33R41 package with two independent reference designators. These reference designators allow two different BSDL files to individually describe the DS33Z41 and DS21458 connections inside the DS33R41 package.

Tables 1, 2, and 3 and Figure 1 make the task of modifying the netlist easy. Table 1 lists all of the external DS33R41 package pins which only connect to the DS33Z41 die. Table 2 lists all of the external DS33R41 package pins which only connect to the DS21458 die. Table 3 lists all of the external DS33R41 package pins which connect to both the DS33Z41 die and the DS21458 die. Figure 1 shows the same information in a format created for easier viewing.

This PWB netlist modification and JTAG boundary scan test have been performed using a Concise Net List format netlist of the DS33R41 engineering evaluation board designed with Cadence® Concept. Designers can perform the operation in approximately 30 to 60 minutes, depending on the netlist type and individual's skill level. Most of the edits to the netlist file can be done with a simple text editor. Depending on the netlist type, however, it may be possible to edit the netlist in a program such as Microsoft® Excel which can sort rows based on column data. However the editing is done, it is important to pay careful attention to detail. Irregular data such as header and footer information must be maintained, and the netlist must always be saved in the original format.

The following is a list of steps needed to complete the process.

1. Open the netlist file in a text editor and group all of the nets connected to the DS33R41 reference designator. As an example, the DS33R41 package on the DS33R41 Engineering Evaluation board had a reference designator of U01.
2. Separate all of the nets isolated in step 1 among those connected to the DS33Z41 die, those connected to the DS21458 die, and those connected to both dies. Use Tables 1, 2, and 3 and Figure 1 to complete this task.
3. Change the reference designator for all of the DS33Z41 nets from U01 to U01_D1 (short for reference designator U01, device 1). This step assumes that the DS33R41 reference designator was U01. If the reference designator is not U01, change U01_D1 appropriately.
4. Change the reference designator for all of the DS21458 nets from U01 to U01_D2 (short for reference designator U01, device 2). This assumes that the DS33R41 reference designator was U01. If it is not U01, change U01_D2 appropriately.
5. Duplicate the 22 shared nets so that there is exactly two of each. Split them into two groups.
6. Change the reference designator for first group of nets created in step 5 from U01 to U01_D1. This assumes that the DS33R41 reference designator was U01. If it is not U01, change U01_D1 appropriately.
7. Change the reference designator for second group of nets created in step 5 from U01 to U01_D2. This assumes that the DS33R41 reference designator was U01. If it is not U01, change U01_D1 appropriately.
8. Save the newly created netlist.

The newly created PCB netlist will actually contain two instances for the DS33R41 physical device. The first instance will describe the pin connections related to the DS33Z41 section; the second will describe pin connections related to the DS21458 section. The new netlist can be loaded into any JTAG test suite along with the two DS33R41 BSDL files and any associated test vectors.

Although the method documented here has been tested and verified to work properly, there can be some unforeseen complications with other netlist formats. If additional assistance is needed during JTAG boundary scan testing, please use the contact information below.

References

If you have additional questions on the JTAG testing of the DS33R41, please contact the Analog Technical support team

For more information about the DS33R41 Inverse-Multiplexing Ethernet Mapper with Integrated Quad Port T1/E1/J1 Transceiver, please consult the appropriate data sheet.