AN-2627: EV-AD74416H-ARDZ EMC Report

Features

EMC robustness testing of the EV-AD74416H-ARDZ

General Description

This application note demonstrates the robustness of the AD74416H during transient immunity testing. Testing is performed, as per the IEC 61000-4-x set of standards, that cover the evaluation of the immunity of electrical and electronic equipment at a system level. The EV-AD74416H-ARDZ evaluation board is characterized to ensure that the circuit performance has sufficient immunity against electrostatic discharge (ESD), electrical fast transients (EFT), and surge.

Summary of Conducted Electromagnetic Compatibility (EMC) Tests

The results of an immunity test are typically classified into four categories, as listed in Table 1. The end-application requirements and their ability to tolerate transient noise determine whether the system sees the specific performance criteria as a failure or not.

Jumper Configurations of the EV-AD74416H-ARDZ

Jumper configurations of the EV-AD74416H-ARDZ during EMC testing are determined by the specific use case being tested. Figure 2 and Figure 3 reflect board jumper configuration options.

Tests Description

ESD

The ESD immunity test emulates the discharges of tens of nanoseconds duration directly on the electronic components. Two discharge methods are used: contact discharge and air discharge. Contact discharge includes a discharge to the conductive surfaces of the device under test (DUT). An ESD test generator is used with a sharp point to make a direct connection to the DUT (pin) for contact ESD testing. A round tip is added to the generator and is brought close to the DUT (pin) to trigger a spark for air-gap ESD testing. The IEC 61000-4-2 test levels are listed in Table 3.

ESD Test Board Setup

There are two methods of applying the discharges: direct and indirect. Direct application involves direct contact to the conductive surfaces and coupling planes. Indirect application involves air discharge at insulating surfaces. The DUT is exposed to at least 20 discharges at each rating for each type of discharge, 10 each at negative and positive polarity. The discharges are repeated at a rate of one discharge per second.

The contact discharges are applied to the contact discharge injection points, depending on the configured mode. Generally, injection points are IO/P_x, IO/N_x, ISN_x, cable shield connection, and horizontal coupling plance (HCP).

The air discharges are applied to the same points as during contact discharge, beside HCP. Those points are IO/P_x, IO/N_x, ISN_x, and shield connection.

The HCP has two 470kΩ bleeding resistors to the ground reference plane (GRP), which is connected to earth ground.

For full schematic setups during ESD testing, see Figure 4 and Figure 5.

ESD Test Results

Table 5 through Table 8 reflect the data gathered during EMC testing and testing results. During each test, ~1000 measurement samples are collected and averaged to determine the impact of the ESD test on the DUT accuracy.

ESD Test Conclusion

The EV-AD74416H-ARDZ has passed the ESD test at maximum ESD Level 4, with ±8kV contact discharge and ±16kV air discharge. The setup takes the higher voltage. However, there is no advantage if it exceeds the maximum level defined by the standard. The system consistently performs to Class B (based on the setup capabilities), and no alerts trigger during reflected ESD tests.

The measurement results and comparison of the performance before (pre) and after (post) ESD striking indicate that the maximum absolute deviation is <60ppmFS, measured by the internal ADC in current mode, with the most common deviation around or lower than 5ppmFS. An absolute current error of <60ppmFS corresponds to <1.5μA absolute difference. When the typical expected system accuracy of approximately 0.1%, the 60ppmFS, 0.006% FS is deemed still well within the AD74416H data sheet specification.

The measurement results of digital output voltage and comparison of the performance before (pre) and after (post) EFT striking indicate that the maximum absolute deviation is <1%, which is still within expected performance of the AD74416H chip.

Based on the results, it is concluded that the AD74416H in the EV-AD74416H-ARDZ system is considered robust from an ESD perspective and passes ESD Level 4, ±8kV contact discharge and ±16kV air discharge, with Class B performance.

Surge EMC Testing

The surge immunity test indicates the capability of the device or equipment to survive surges caused by events, such as lightning strikes or industrial power surges caused by switching heavy loads or short-circuit fault conditions.

Per the IEC 61000-4-5 standard for industrial environments, the surge is a combination wave of 1.2μs rising time with 50μs pulse width open circuit voltage and 8μs rising time with 20μs pulse width short-circuit current. The DUT is subject to five positive and five negative surges at each rating. The interval between each surge is 1 min.

Surge Test Board Setup

The surge is tested on the AD74416H output cable, which is treated as both unshielded asymmetrically and symmetrically operated interconnection lines of the DUT. The surge is applied to the input/output (I/O) and sense lines through coupling decoupling network (CDN) 117.

Surge Test Results

Table 11 through Table 14 reflect the data gathered during EMC testing and testing results. During each test, ~1000 measurement samples are collected and averaged to determine the impact of the surge test on the DUT accuracy.

Surge Test Conclusion

The EV-AD74416H-ARDZ has passed the surge test with maximum surge Level 2, ±1.2kV.

The measurement results of voltage output and comparison of the performance before (pre) and after (post) surge striking indicate that the maximum absolute deviation is <10ppmFS, with most common deviation around or lower than 4ppmFS.

During differential surge voltage output testing, ADC saturation error has been flagged. This poses no concern as a high-voltage spike is directly injected into the ADC input (via protection resistors). During the strike, the voltage measured by ADC is temporarily higher than the ADC range (±12V).

The measurement results of digital output voltage and comparison of the performance before and after surge striking indicate that the maximum absolute deviation is <0.5%, with most common deviation around or lower than 0.1%.

Based on the results, it is concluded that the AD74416H in the EV-AD74416H-ARDZ system is considered robust from a surge perspective and passes Level 2, ±1.2kV, Class B performance.

EFT EMC Testing

Per the IEC 61000-4-4 standard, the DUT is tested with 2000V discharges on the analog input cable. Positive and negative polarity discharges are applied. The duration time of each test is 1 min. The transient and burst waveform is in accordance with IEC 61000-4-4, with a 5ns rising time and a 50ns pulse width. Both 5kHz and 100kHz repetition frequencies are used for the test. The configuration consists of a 0.8-meter high wooden table, covered with a sheet of copper that is at least 0.25mm thick, and connected to the protective grounding system. The DUT is placed on a 0.1-meter thick isolating support. A minimum distance of 0.5 meter is provided between the DUT and the walls of the laboratory.

EFT Test Board Setup

The EFT test utilizes a cable clamp to inject the signal onto the DUT cable. Representative modes of operation for the AD74416H are selected to ensure the robustness of individual blocks within the DUT during EFT testing.

For full schematic setups during ESD testing, see Figure 8 and Figure 9.

EFT Test Results

Table 17 through Table 21 reflect the data gathered during EMC testing and testing results. During each test, ~1000 measurement samples are collected and averaged to determine the impact of the EFT test on the DUT accuracy. During the digital input and digital output testing, the digital counter is enabled, and the counter readings before and after the test are evaluated.

EFT Test Conclusion

The EV-AD74416H-ARDZ has passed EFT test with maximum EFT Level 4, ±2kV.

The measurement results and comparison of the performance before (pre) and after (post) EFT striking indicate that the maximum absolute deviation is <10ppmFS, with most common deviation around or lower than 4ppmFS.

The measurement results of digital output voltage and comparison of the performance before and after EFT striking indicate that the maximum absolute deviation is <0.1%.

During both digital input and digital output testing, input counter is enabled to ensure that DUT is monitored during the EFT testing.

Input voltage comparator is set to 8V and any debounce time is bypassed to reliable detect any change on the screw terminal. There is no difference in the counter count before and after the testing. This results to uninterrupted operation even during the EFT testing, reaching Class A performance for these modes.

Based on the results, it is concluded that the AD74416H in the EV-AD74416H-ARDZ system is considered robust from a EFT perspective and passes Level 4, ±2kV, Class A performance for digital output and digital input modes and Class B performance for other modes.