AN-2612: Modes of Operation with Changes in Interframe Gap (IFG)

Background

This application note describes the fido5200/fido5210 (hereafter referred to as FIDO52x0) performance when different interframe gaps (IFG) occur and makes recommendations on how best to set up the device for these scenarios.

The FIDO52x0 is a real-time Ethernet, multiprotocol (REM), two-port switch. The REM switch provides customers the flexibility to select processors that best fit the application. The switch offers 10Mbps/100Mbps throughput and supports most Layer 2 or Layer 3 protocols. The FIDO52x0 supports EtherCAT as well as PROFINET real-time (RT) and isochronous real-time (IRT), EtherNet/IP with and without device level ring (DLR), Modbus TCP, and POWERLINK. The switch contains software drivers for each protocol. The software drivers provide an API for integration with any field device or protocol stack.

IFG Configuration

The IEEE 802.3 Ethernet standard calls for an IFG of 12 byte times. This was the default IFG supported by FIDO52x0. However, the EtherCAT Technical Group (ETG) allows for the IFG to fall below this. The FIDO52x0 firmware has been modified to support an IFG as low as 8 byte times.

The RX IFG to be counted by FIDO52x0 on the ingress data can be configured using the RX IFG register. The RX IFG is counted in the RX MAC. The register value must be set to the desired RX IFG-1. Thus, to support an RX IFG of 12, the RX IFG count must be set to 11. Note, if incoming data has an IFG less than the value programmed in RX IFG then FIDO52x0 drops the frame.

The minimum gap between outgoing packets can be configured using the TX IFG register. The TX IFG is enforced in TX MAC. The outgoing IFG is not less than the value in the TX IFG register.

Note, to avoid RX buffer overflow, it is important that RX and TX IFG minimums be balanced for proper operation. Balanced, in the case of requiring an IFG of 12, means setting RX IFG to 11 and TX IFG to 12. In this scenario, if FIDO52x0 counts an RX IFG of only 11, it restores the IFG to 12 at the TX.

Hardware Synchronization

Figure 1 shows a block diagram of the synchronization blocks of the FIDO52x0.

The 25MHz RXCLK and RX_DV signals are consumed and synchronized into the 125MHz clock space. The MAC detects the rising edge of RX_DV and start of frame delimiter (SFD) and passes this information to the packet processing logic. Depending on where the 25MHz and 125MHz clock edges occur with respect to each other, there is an opportunity for a +0/–1 RXCLK time (1/25MHz = 40ns) jitter relative to the 125MHz clock phase. Packet processing occurs in the 125MHz system clock space (center block in Figure 1). The outgoing data is synchronized into the TXCLK (25MHz) space. This creates the possibility of a nibble-time loss (40ns) in synchronization which is primarily a function of the phase relationship between the three clocks and the execution state of the packet handler between incoming packets.

Real World Use Case

An Analog Devices, Inc. customer, developing a transducer device, encountered an issue in a network with a mix of different devices where the transducer device started to drop frames. A timing examination discovered that the IFG at the RX was 9 byte times when RX IFG of the FIDO52x0 was configured to 10 byte times and TX IFG was configured to 11 byte times. When RX IFG is less than the value configured in FIDO52x0, the switch drops the frame automatically. Reconfiguring the RX IFG register to 7 and the TX IFG register to 8 resolved the issue. The device was subsequently tested in a large network of devices with no issues reported. It was documented that there were 87 devices in the network. It was verbalized to Analog Devices that there were 127 devices in the network.