Smart GaN Buck Controller Designs—Part 2: Configuration and Optimization

Question:

What is the impact of using a 35 ns dead time in R_SET mode on the thermal performance of the GaN FETs compared to the smart near-zero dead time mode?

Smart GaN Buck Controller Designs—Part 2: Configuration and Optimization

Answer:

When using a 35 ns dead time in R_SET mode, both the top and bottom GaN FETs experience a significant temperature increase when compared to thermal increase in the smart near-zero dead time mode under identical operating conditions. This temperature rise is due to the larger reverse conduction losses associated with GaN FET physical properties, which reduces efficiency and increases thermal stress on the FETs. If a longer dead time is chosen, it becomes absolutely essential to optimize the pull-up and pull-down resistance to achieve the lowest possible transition losses while still meeting the overshoot and undershoot specs of the FET at the fastest possible slew rate. Otherwise, too much output power capacity will be given up to maintain safe thermal operating margins.

Introduction

In the first part of this series, the importance of understanding the underlying physics of switching supplies and how to properly physically measure their consequences was discussed. Once a circuit has been set up on a lab bench, the real work begins. Unlike monolithic IC designs, controllers are made to drive a wide range of switch devices and must therefore be tuned to some degree to ensure optimal performance. If the measurement technique is no longer in question, the gate and switch waveforms provide valuable information on what component values need to be modified to prevent damage to the gallium nitride (GaN) FETs and extract the most efficient operation possible.

Taming the Gate Connection

To snub the peak overshoot, increase the value of the gate pull-up resistor. If the gate is slow rising and has no overshoot, this will not damage the FET, but the controller will delay turn-on or turn-off to maintain the programmed dead time, which causes increased transition losses associated with excessive gate resistance. To correct for this, decrease the gate pull-up resistor. See Figure 1 to understand the impact that gate resistance has on the waveform. The top trace shows gate measurements with pure PCB trace—effectively 0 Ω of pull-up and pull-down resistance on the top and bottom gates (TG and BG traces). The lower trace shows 10 Ω of both the pull-up and pull-down resistance for both the top and bottom gates. Recalling that ideal switching involves instantaneous transitions, a fast-rising waveform with a small amount of overshoot within limits over the entire input voltage and output current range is preferable to an excessively damped gate waveform. The gate falling waveform overshoot is similarly adjusted by increasing or decreasing the gate pull-down resistor. The center trace shows a decent compromise between the overshoot associated with 0 Ω, and the excessive delays to eliminate all over/undershoot of 10 Ω. A key advantage to split pull-up/pull-down lines is the ability to tailor each resistance. Note that 2 Ω of pull-up resistance in the center trace of Figure 1 sufficiently damps the overshoot, but as little as 1 Ω of pull-down resistance in Figure 2 is needed to correct the undershoot shown in the top traces of both the top and bottom gates.

Figure 1. The effect of series resistance on gate slew (SW rising) TG: top gate; BG: bottom gate. The top figure shows PCB trace for gate connection (0 Ω). The middle figure shows optimized gate resistance. The bottom figure shows all gates with 10 Ω in series with gate drive pins. The most critical value for the SW node rising is R_TGPULL-UP.

Figure 2. The effect of series resistance on gate slew (SW falling) TG: top gate; BG: bottom gate. The top figure shows the PCB trace for gate connection (0 Ω). The middle figure shows the optimized gate resistance. The bottom figure shows all gates with 10 Ω in series with gate drive pins. The most critical value for the SW node falling is R_TGPULL-DOWN.

Poor layout or overly conservative damping with gate resistance comes at a price. The longer the transition takes—even with near-zero dead time guaranteed from a threshold point of view—the more transition losses will eat into the efficiency budget. This is confirmed by thermal analysis using the FLIR imaging unit. This is illustrated very dramatically in Figure 3, which shows a near 40°C temperature rise between 0 Ω and 10 Ω resistors measured in the previous figures. This represents a loss in the available power budget before allowable thermal stress on the FETs is exceeded. Another concern to look for with the bottom gate is phantom turn-on, which will appear to be a swell in the ringing that begins to approach threshold voltages of the bottom FET; having both FETs on is never a good thing! The LTC7890 and LTC7891 have low impedance gate drivers that help prevent this, but bottom gate pull-down resistance should be optimized with this in mind. This process of optimizing gate drive levels ensures that the FETs will be safely switched under all conditions using smart near-zero dead time, but how should other modes or dead times be verified?

Figure 3. Thermal capture of transition losses due to gate resistance. The top image is taken at 24 V_IN and 12 V_OUT at 10 A using PCB trace resistance on all gate traces, resulting in a peak temperature of 52.1°C on the top FET. The bottom image shows identical conditions with 10 Ω of resistance on all gate traces. The top FET increases to 93.4°C with no additional power at the output.

Choosing the Dead Time Delay

In some cases, a designer may choose or be mandated to use a set amount of dead time. The LTC7890 and LTC7891 have three modes of dead time control, summarized in Table 1. Smart near-zero dead time servos the appropriate gate to ensure no destructive levels of energy remain with such tight timing. Adaptive gate-to-gate dead time uses Kelvin-sensed thresholds present at the gates themselves to servo timing to a default of 20 ns dead time. R_SET programmable dead time uses the same internal logic but allows a trimmed precision offset of the 20 ns value from 7 ns to 60 ns. If either of these two other configurations are used, it will be necessary to set trigger thresholds at 1 V using the gate signals to verify the timing is functioning as programmed.

Table 1. DTC Mode Configuration
Dead Time Control (DTC) Mode	DTCA	DTCB	Dead Time (ns)
Smart Near-Zero DTC	INTV_CC		0 (typ)
Adaptive DTC	GND		20 (typ)
R_SET DTC	10 Ω to 200 kΩ	10 Ω to 200 kΩ	7 to 60

Choosing a dead time is an exercise in trade-offs. For the lowest losses possible, use the smart near-zero dead time and rely on the intelligent detection and servo architecture for the highest possible power density applications with the highest efficiency. Armed with the knowledge of how to set up and verify the dead time is minimized to near zero with proper measurements, this is generally the best option. Figure 4 shows this near-zero dead time in action with optimized gate resistance. There is no visible reverse conduction time, and no parallel Schottky diode is used at additional penalty to protect the GaN FET. This results in maximum efficiency and minimal thermal stress. If, however, design mandates dictate some finite amount of dead time beyond this, the adaptive modes will allow any value to be dialed in for perceived comfort margin at the expense of power lost to heat in the GaN FETs, as shown in Figure 5. This may be due to conservative management engineering mandates or driven by reluctance to stray too far from guidance derived from MOSFET-based designs, but the LTC7890 and LTC7891 allow the user all options to suit their needs. As dead times increase, it is especially important to record efficiency and peak hot spot temperatures of the FETs with thermal imaging devices at the corner conditions to retain thermal margin for planned ambient operating conditions. Like the gate resistance, dead time has a direct and pronounced effect on peak thermal stress on the FETs. The peak temperature of the top FET for the 12 V_OUT, 10 A condition being tested here is 56.3°C using the optimized gate resistances. This represents a 3°C temperature rise from the 0 Ω PCB trace, but reasonable considering there is no overvoltage stress to damage the FETs during transients. However, when the R_SET mode is used to increase the dead time to the 35 ns typically found in controllers without smart near-zero or adaptive controls, this jumps over 10°C to 66.5°C for the same power developed at the output—and it’s seen on both FETs (Figure 6). It becomes apparent that the price for being conservative in this regard is an efficiency and thermal penalty that eats into the power budget. That same amount of thermal loss could have been used for an additional several dozen watts of output power delivery if the smart near-zero functionality had been utilized. Food for thought when deciding if tradition, rather than empirical data, is to be prioritized when determining dead time margin for comfort.

Figure 4. Smart near-zero dead time control transitions using optimized gate resistance. Note there is no visible reverse conduction region showing on switch node with this mode enabled to actively control dead time.

Figure 5. 35 ns dead time R_SET mode transitions using optimized gate resistance. The dead time is precisely controlled but the reverse conduction periods reflected in the switching waveforms are clearly visible at 2 V, resulting in considerable losses.

Figure 6. Thermal capture of transition losses due to dead time modes. The top image is taken at 24 V_IN and 12 V_OUT at 10 A using smart near-zero dead time mode and optimized gate resistance, resulting in a peak temperature of 56.3°C on the top FET. The bottom image shows identical conditions with 35 ns (typical) dead time configured in R_SET mode. Both FETs increase in temperature to 66.5°C with no additional power delivered at the output.

Follow this development process by starting with a sound layout using evaluation reference designs provided by Analog Devices. Continue with solid bench measurement techniques to measure and validate the design. This ultimately results in a reliable design circuit for the final product. The data collected during this process, following the procedures and techniques described, will be accurate and trustworthy. Armed with a solid understanding of what the trade-offs are and how to balance them, better decisions about which modes of operation, what external component values to use—and, more importantly, why those decisions are being made—will ultimately shorten design cycle times, reduce costly iterations, and prevent much frustration by the system designer.

Conclusion

GaN technology is rapidly developing as leaders in the wide band gap technology continue to improve the C_G × R_DS(ON) figure of merit with each generation of device offerings. While the device size, capacitance, and on-resistance change with each new iteration, the right approach to reliable measurement and verification of operation remains the same. There is simply no acceptable substitute for bench verification of prototype operation to ensure that a design is solid and has sufficient safety margin at the corner conditions of operation. Designs that follow data sheet guidelines, layouts that closely follow evaluation board placement and routing, and measurements taken with the guidance offered here will offer the best chances of a first pass success with no re-spin necessary.