MAX9381

PRODUCTION

Lowest Power 3.0GHz ECL/PECL Differential Data and Clock D Flip-Flop

Viewing:

Overview

  • 3.0GHz Guaranteed Operating Clock Frequency
  • 0.2psRMS Added Random Jitter
  • 328ps Typical Propagation Delay
  • PECL Operation from VCC = 2.25V to 5.5V with VEE = 0V
  • ECL Operation from VEE = -2.25V to -5.5V with VCC = 0V
  • Input Safety Clamps Ensure Output Stability when Inputs are Open or at VEE
  • ±2kV ESD Protection (Human Body Model)
  • The MAX9381 differential data, differential clock D flip-flop is pin compatible with the ON Semiconductor MC100EP52, with the added benefit of a wider supply-voltage range from 2.25V to 5.5V and 25% lower supply current. Data enters the master part of the flip-flop when the clock is low and is transferred to the outputs upon a positive transition of the clock. Interchanging the clock inputs allows the part to be used as a negative edge-triggered device. The MAX9381 utilizes input clamping circuits that ensure the stability of the outputs when the inputs are left open or at VEE.

    The MAX9381 is offered in an 8-pin SO package and the smaller 8-pin µMAX package.

    Applications

    • Automated Test Equipment (ATE)
    • Central Office Telecom Equipment
    • DLCs
    • DSLAM
    • Precision Clock and Data Distribution
    • Wireless Base Stations

    MAX9381
    Lowest Power 3.0GHz ECL/PECL Differential Data and Clock D Flip-Flop
    MAX9381: Functional Diagram
    Add to myAnalog

    Add product to the Products section of myAnalog (to receive notifications), to an existing project or to a new project.

    Create New Project
    Ask a Question

    Documentation

    Learn More
    Add to myAnalog

    Add media to the Resources section of myAnalog, to an existing project or to a new project.

    Create New Project

    Tools & Simulations

    Latest Discussions

    Recently Viewed