MAX9326

1:9 Differential LVPECL/LVECL/HSTL Clock and Data Driver

Data Sheet (Rev. 2)

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Overview

50ps (max) Output-to-Output Skew

1.5ps_RMS (max) Random Jitter

Guaranteed 300mV Differential Output at 1.0GHz

+2.375V to +3.8V Supplies for Differential HSTL/LVPECL

-2.375V to -3.8V Supplies for Differential LVECL

On-Chip Reference for Single-Ended Inputs

Outputs Low for Inputs Open or at V_EE

Pin Compatible with MC100LVE111

The MAX9326 low-skew, 1:9 differential driver features extremely low output-to-output skew (50ps max) and part-to-part skew (225ps max). These features make the device ideal for clock and data distribution across a backplane or board. The device repeats an HSTL or LVECL/LVPECL differential input at nine differential outputs. Outputs are compatible with LVECL and LVPECL, and directly drive 50Ω terminated transmission lines.

The differential inputs can be configured to accept a single-ended signal when the unused complementary input is connected to the on-chip reference output voltage V_BB. All inputs have internal pulldown resistors to V_EE. The internal pulldowns and a fail-safe circuit ensure differential low default outputs when the inputs are left open or at V_EE.

The MAX9326 operates over a +2.375V to +3.8V supply range for interfacing to differential HSTL and LVPECL signals. This allows high-performance clock or data distribution in systems with a nominal +2.5V or +3.3V supply. For LVECL operation, the device operates with a -2.375V to -3.8V supply.

The MAX9326 is offered in 28-lead PLCC and space-saving 28-lead QFN packages. The MAX9326 is specified for operation from -40°C to +85°C.

Applications