MAX3991

10Gbps Clock and Data Recovery with Limiting Amplifier

10Gbps Clock and Data Recovery (CDR) with Limiting Amplifier IC for XFP Optical Receivers

Data Sheet (Rev. 1)

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Overview

Multirate Operation from 9.95Gbps to 11.1Gbps

7mV_P-P Input Sensitivity (BER < 10^-12)

0.6UI_P-P Total High-Frequency Jitter Tolerance

Low-Output Jitter Generation: 7mUI_RMS

Low-Output Deterministic Jitter: 4.6ps_P-P

XFI-Compliant Output Interface

LOS Indicator with Programmable Threshold

LOL Indicator

Power Dissipation: 350mW

The MAX3991 is a 10Gbps clock and data recovery (CDR) with limiting amplifier IC for XFP optical receivers. The MAX3991 and the MAX3992 (CDR with equalizer) form a signal conditioner chipset for use in XFP transceiver modules. The chipset is XFI compliant and offers multirate operation for data rates from 9.95Gbps to 11.1Gbps.

The MAX3991 has 7mV_P-P input sensitivity (BER < 10^-12), which allows direct connection to a transimpedance amplifier without the use of a stand-alone limiting amplifier. The phase-locked loop (PLL) is optimized for jitter tolerance and provides 0.6UI of high-frequency tolerance in SONET, Ethernet, and Fibre-Channel applications. The MAX3991 output provides 27% margin to the XFP eye mask specification.

An AC-based power detector toggles the loss-of-signal (LOS) output when the input signal swing is below the user-programmed assert threshold. An external reference clock, with frequency equal to 1/64 or 1/16 of the serial data rate is used to aid in frequency acquisition. A loss-of-lock (LOL) indicator is provided to indicate the lock status of the receiver PLL.

The MAX3991 is available in a 4mm x 4mm, 24-pin QFN package. It consumes 350mW from a single +3.3V supply and operates over the 0°C to +85°C temperature range.

Applications