MAX3620

Delay Lines for High-Speed Clock Distribution Systems

Data Sheet (Rev. 0)
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Overview

  • Supports HSTL Source Terminated Lines
  • All-Passive Design
  • Compatible with 100Ω Differential and 50Ω Single- Ended Transmission Lines
  • Small 3mm x 3mm Package

    • The MAX3620 series is a family of high-performance passive delay lines for use in QDR/QDRII synchronous memory systems. These delay lines support high-speed transceiver logic (HSTL) source terminated transmission with an unterminated load at the receiver, and deliver accurate delays of 0.75ns, 1.00ns, 1.25ns, and 1.50ns for the generation of the quarter clock phase. The MAX3620 is offered in a small 3mm x 3mm package which contains two delay lines of equal length that can be driven either differentially or single-endedly.

    Applications

    • Multiphase Clock Generation
    • QDR/QDRII Memory Systems
    MAX3620
    Delay Lines for High-Speed Clock Distribution Systems
    MAX3620: Typical Operating Circuit
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    Documentation

    Data Sheet 1

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