DS2156L

T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface

Industry's First T1/E1/J1 Transceiver for ATM Applications

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Part Details

  • Complete T1/DS1/ISDN-PRI/J1 transceiver functionality
  • Complete E1 (CEPT) PCM-30/ISDN-PRI transceiver functionality
  • User-selectable TDM or UTOPIA II bus interface
  • Long-haul and short-haul line interface for clock/data recovery and waveshaping
  • CMI coder/decoder for optical I/F
  • Crystal-less jitter attenuator
  • Fully independent transmit and receive functionality
  • Dual HDLC controllers
  • Programmable BERT generator and detector
  • Internal software-selectable receive and transmit-side termination resistors for 75Ω/100Ω/120Ω T1 and E1 interfaces
  • Dual two-frame elastic-store slip buffers that connect to asynchronous backplanes up to 16.384MHz
  • 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz clock output synthesized to recovered network clock
  • Additional features listed in full data sheet
DS2156L
T1/E1/J1 Single-Chip Transceiver TDM/UTOPIA II Interface
DS2156, DS2156L, DS2156LN: Block Diagram
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Hardware Ecosystem

Parts Product Life Cycle Description
Product 4
DS21352 NOT RECOMMENDED FOR NEW DESIGNS 3.3V DS21352 and 5V DS21552 T1 Single Chip Transceivers
DS21354 NOT RECOMMENDED FOR NEW DESIGNS 3.3V/5V E1 Single Chip Transceivers (SCT)
DS21552 NOT RECOMMENDED FOR NEW DESIGNS 3.3V DS21352 and 5V DS21552 T1 Single Chip Transceivers
DS21554 NOT RECOMMENDED FOR NEW DESIGNS 3.3V/5V E1 Single Chip Transceivers (SCT)
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