DS1743
Y2K-Compliant, Nonvolatile Timekeeping RAMs
Overview
- Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit, and Lithium Energy Source
- Clock Registers are Accessed Identically to the Static RAM. These Registers Reside in the Eight Top RAM Locations.
- Century Byte Register
- Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power
- BCD-Coded Century, Year, Month, Date, Day, Hours, Minutes, and Seconds with Automatic Leap Year Compensation Valid through 2099
- Low-Battery-Voltage Level Indicator Flag
- Power-Fail Write Protection Allows for ±10% VCC Power-Supply Tolerance
- Lithium Energy Source is Electrically Disconnected to Retain Freshness Until Power is Applied for the First Time
- DIP Module Only
- Standard JEDEC Bytewide 8k x 8 Static RAM Pinout
- PowerCap Module Board Only
- Surface-Mountable Package for Direct Connection to PowerCap Containing Battery and Crystal
- Replaceable Battery (PowerCap)
- Power-On Reset Output
- Pin-for-Pin Compatible with Other Densities of DS174XP Timekeeping RAM
The DS1743 is a full-function, year-2000-compliant (Y2KC), real-time clock/calendar (RTC) and 8k x 8 nonvolatile static RAM. User access to all registers within the DS1743 is accomplished with a bytewide interface as shown in Figure 1 in the full data sheet. The RTC information and control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour binary-coded decimal (BCD) format. Corrections for the day of the month and leap year are made automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1743 also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out-of-tolerance condition. When VCC is above VPF, the device is fully accessible. When VCC is below VPF, the internal active-low CE signal is forced high, preventing any access. When VCC rises above VPF, access remains inhibited for TREC, allowing time for the system to stabilize. These features prevent loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided.
Documentation
Data Sheet 1
Reliability Data 1
Design Note 4
Technical Articles 2
This is the most up-to-date revision of the Data Sheet.
Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Memory & Data Loggers 1 | ||
| DS9034PCX | PowerCap with Crystal | |
Tools & Simulations
IBIS Model 1
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