DS1647P
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DS1647P

Nonvolatile Timekeeping RAM

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Features
  • Integrates NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit, and Lithium Energy Source
  • Clock Registers Are Accessed Identically to the Static RAM. These Registers are Resident in the Eight Top RAM Locations.
  • Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power
  • BCD Coded Year, Month, Date, Day, Hours, Minutes, and Seconds with Leap Year Compensation Valid Through 2099
  • Power-Fail Write Protection Allows for ±10% VCC Power-Supply Tolerance
  • DS1647 Only (DIP Module):
    • Standard JEDEC Byte-Wide 128k x 8 RAM Pinout
  • DS1647P Only (PowerCap Module Board):
    • Surface Mountable Package for Direct Connection to PowerCap Containing Battery and Crystal
    • Replaceable Battery (PowerCap)
    • Power-Fail Output
    • Pin-for-Pin Compatible with Other Densities of DS164xP Timekeeping RAM
Additional Details
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The DS1647 is a 512k x 8 nonvolatile static RAM with a full-function real-time clock, which are both accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to any JEDEC standard 512k x 8 SRAM. The device can also be easily substituted for ROM, EPROM and EEPROM, providing read/write nonvolatility and the addition of the real-time clock function. The real-time clock information resides in the eight uppermost RAM locations. The RTC registers contain year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year are made automatically. The RTC clock registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1647 also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out-of-tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided.

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