DS1643P
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DS1643P

Nonvolatile Timekeeping RAM

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Features
  • Integrated NV SRAM, Real-Time Clock, Crystal, Power-Fail Control Circuit and Lithium Energy Source
  • Clock Registers are Accessed Identically to the Static RAM. These Registers Reside in the Eight Top RAM Locations
  • Totally Nonvolatile with Over 10 Years of Operation in the Absence of Power
  • Access Times of 85ns and 100ns
  • BCD-Coded Year, Month, Date, Day, Hours, Minutes, and Seconds with Leap Year Compensation Valid Up to 2100
  • Power-Fail Write Protection Allows for ±10% VCC Power Supply Tolerance
  • Lithium Energy Source is Electrically Disconnected to Retain Freshness Until Power is Applied for the First Time
  • DS1643 Only (DIP Module)
    • Standard JEDEC Byte-Wide 8K x 8 RAM Pinout
    • DS1643P Only (PowerCap Module Board)
      • Surface Mountable Package for Direct Connection to PowerCap Containing Battery and Crystal
      • Replaceable Battery (PowerCap)
      • Power-Fail Output
      • Pin-for-Pin Compatible with Other Densities of DS164XP Timekeeping RAM
Additional Details
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The DS1643 is an 8K x 8 nonvolatile static RAM with a full function Real Time Clock (RTC) that are both accessible in a byte-wide format. The nonvolatile timekeeping RAM is functionally equivalent to any JEDEC standard 8K x 8 SRAM. The device can also be easily substituted in ROM, EPROM and EEPROM sockets providing read/write nonvolatility and the addition of the real time clock function. The real time clock information resides in the eight uppermost RAM locations. The RTC registers contain year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year are made automatically. The RTC clock registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles. The double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. The DS1643 also contains its own power-fail circuitry, which deselects the device when the VCC supply is in an out of tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low VCC as errant access and update cycles are avoided.

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