Overview

Features and Benefits

  • Integrated Real-Time Clock (RTC), Power-Fail Control Circuit, and NV RAM Controller
  • Clock Registers are Accessed Identically to the Static RAM; These Registers are Resident in the 16 Top RAM Locations
  • Century Register
  • Greater than 10 Years of Timekeeping and Data Retention in the Absence of Power with Small Lithium Coin Cell(s) and Low-Leakage SRAM
  • Precision Power-On Reset
  • Programmable Watchdog Timer and RTC Alarm
  • BCD-Coded Year, Month, Date, Day, Hours, Minutes, and Seconds with Automatic Leap-Year Compensation Valid Up to the Year 2100
  • Battery Voltage-Level Indicator Flag
  • Power-Fail Write Protection Allows for ±10% VCC Power-Supply Tolerance

Product Details

The DS1558 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar with an RTC alarm, watchdog timer, power-on reset, battery monitor, and NV SRAM controller. User access to all registers within the DS1558 is accomplished with a byte-wide interface as shown in Figure 1. The RTC registers contain century, year, month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for day of month and leap year are made automatically.

The DS1558 maps the RTC registers into the SRAM address space and constantly monitors A0-A18. When any of the upper 16 address locations are accessed, the DS1558 inhibits active-low CER and active-low OER to the SRAM, and redirects reads and writes to the RTC registers within the DS1558. The DS1558 can be used with SRAMs up to 524,272 addresses. Smaller SRAMs can be used, provided that the unused upper address lines on the DS1558 are connected to VCC.

The RTC registers are double-buffered into an internal and external set. The user has direct access to the external set. Clock/calendar updates to the external set of registers can be disabled and enabled to allow the user to access static data. Assuming the internal oscillator is turned on, the internal set of registers is continuously updated; this occurs regardless of external register settings to guarantee that accurate RTC information is always maintained.

The DS1558 has interrupt (active-low IRQ/FT) and reset (active-low RST) outputs that can be used to control CPU activity. The active-low IRQ/FT interrupt output can generate an external interrupt when the RTC register values match user-programmed alarm values. The interrupt is always available while the device is powered from the system supply, and it can be programmed to occur when in the battery-backed state to serve as a system wake-up. The active-low IRQ/FT output can also be used as a CPU watchdog timer. CPU activity is monitored and an interrupt or reset output is activated if the correct activity is not detected within programmed limits. The DS1558 power-on reset can be used to detect a system power-down or failure and hold the CPU in a safe reset state until normal power returns and stabilizes; the active-low RST output is used for this function.

The DS1558 also contains its own power-fail circuitry, which automatically protects the data in the clock and SRAM against out-of-tolerance VCCI conditions by inhibiting the active-low CE input when the VCC supply enters an out-of-tolerance condition. When VCCI goes below the level of VBAT, the external battery is switched on to supply energy to the clock and the external SRAM. This feature provides a high degree of data security during unpredictable system operation brought on by low VCC levels.

Product Lifecycle icon-recommended Production

At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.

Product Recommendations

DS1558 Companion Parts

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Design Resources

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.

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