ADuM263N
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ADuM263N

Robust 5.0 kVrms Six Channel Digital Isolator w/ Fail-Safe & 3 Reverse Channels

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Info: : PRODUCTION tooltip
Info: : PRODUCTION tooltip
Part Details
Part Models 4
1ku List Price Starting From $2.36
Features
  • High common-mode transient immunity: 100 kV/μs
  • High robustness to radiated and conducted noise
  • Low propagation delay
    • 13 ns maximum for 5 V operation
    • 15 ns maximum for 1.8 V operation
  • 150 Mbps maximum guaranteed data rate
  • Safety and regulatory approvals
    • UL recognition: 5000 V rms for 1 minute per UL 1577
    • CSA Component Acceptance Notice 5A
    • VDE certificate of conformity
      • DIN V VDE V 0884-11:2017-01
      • VIORM = 849 V peak
    • CQC certification per GB4943.1-2011
  • Low dynamic power consumption
  • 1.8 V to 5 V level translation
  • High temperature operation: 125°C
  • Fail-safe high or low options
  • 16-lead, RoHS-compliant, wide body SOIC_IC package
Additional Details
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The ADuM260N/ADuM261N/ADuM262N/ADuM263N1 are 6-channel digital isolators based on Analog Devices, Inc., iCoupler® technology. Combining high speed, complementary metal-oxide semiconductor (CMOS) and monolithic air core transformer technology, these isolation components provide outstanding performance characteristics superior to alternatives such as optocoupler devices and other integrated couplers. The maximum propagation delay is 13 ns with a pulse width distortion of less than 4.5 ns at 5 V operation. Channel to channel matching of propagation delay is tight at 4.0 ns maximum.

The ADuM260N/ADuM261N/ADuM262N/ADuM263N data channels are independent and are available in a variety of configurations with a withstand voltage rating of 5.0 kV rms (see the Ordering Guide in the data sheet). The devices operate with the supply voltage on either side ranging from 1.7 V to 5.5 V, providing compatibility with lower voltage systems as well as enabling voltage translation functionality across the isolation barrier.

Unlike other optocoupler alternatives, dc correctness is ensured in the absence of input logic transitions. Two different fail-safe options are available by which the outputs transition to a predetermined state when the input power supply is not applied.

APPLICATIONS

  • General-purpose multichannel isolation
  • Serial peripheral interface (SPI)/data converter isolation
  • Industrial field bus isolation

1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Part Models 4
1ku List Price Starting From $2.36

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Documentation

Documentation

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Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
ADUM263N0BRIZ
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ADUM263N0BRIZ-RL
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ADUM263N1BRIZ
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ADUM263N1BRIZ-RL
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Software & Part Ecosystem

Software & Part Ecosystem

Evaluation Kit

Evaluation Kits 1

reference details image

EVAL-5CH6CHEBZ

Evaluation Board for Five and Six Channel Standard Data Isolators in 8 lead SOIC

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EVAL-5CH6CHEBZ

Evaluation Board for Five and Six Channel Standard Data Isolators in 8 lead SOIC

Evaluation Board for Five and Six Channel Standard Data Isolators in 8 lead SOIC

Features and Benefits

  • Access to 6 data channels
  • Multiple connection options
  • Support for active probes
  • Provisions for cable terminations
  • Support for printed circuit board (PCB) edge mounted coaxial connectors
  • Easy configuration

Product Detail

The EVAL-5CH6CHSOICEBZ supports 5-channel and 6-channel iCoupler® standard data isolators in a 16-lead SOIC package. The evaluation board provides a JEDEC standard, 16-lead SOIC_N and SOIC_W pad layout. This layout supports signal distribution, loopback, and loads referenced to the VDDx or GNDx planes, as well as optimal bypass capacitance. Signal sources can be conducted to the evaluation board through header pins or through edge mounted SMA connectors (SMA connectors must be ordered separately). Screw terminal blocks on the evaluation board provide power connections.

The evaluation board includes 0.2 inch header positions for compatibility with active probes (probe header pins must be ordered separately).

The evaluation board follows best PCB design practices for 4-layer boards, including a full power plane and ground plane on each side of the isolation barrier. No other electromagnetic interference (EMI) or noise mitigation design features are included on the evaluation board. In cases of high speed operation, or when ultralow emissions are required, refer to the AN-1109 Application Note for additional evaluation board layout techniques.

Tools & Simulations

Tools & Simulations 1

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