ADN4667

PRODUCTION

3 V LVDS Quad CMOS Differential Line Driver

Data Sheet (Rev. B) Product Selection Table
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Overview

  • ±15 kV ESD protection on output pins
  • 400 Mbps (200 MHz) switching rates
  • Flow-through pinout simplifies PCB layout
  • 300 ps typical differential skew
  • 400 ps maximum differential skew
  • 1.7 ns maximum propagation delay
  • 3.3 V power supply
  • See Data Sheet for Additional Information

The ADN4667 is a quad, CMOS, low voltage differential signaling (LVDS) line driver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. It features a flow through pinout for easy PCB layout and separation of input and output signals.

The device accepts low voltage TTL/CMOS logic signals and converts them to a differential current output of typically ±3.1 mA for driving a transmission medium such as a twisted pair cable. The transmitted signal develops a differential voltage of typi- cally ±310 mV across a termination resistor at the receiving end. This is converted back to a TTL/CMOS logic level by an LVDS receiver, such as the ADN4668.

The ADN4667 also offers active high and active low enable/ disable inputs (EN and EN). These inputs control all four drivers and turn off the current outputs in the disabled state to reduce the quiescent power consumption to typically 10 mW.

The ADN4667 and its companion LVDS receiver, the ADN4668, offer a new solution to high speed, point-to-point data trans- mission, and a low power alternative to emitter-coupled logic (ECL) or positive emitter-coupled logic (PECL).

Applications

  • Backplane data transmission
  • Cable data transmission
  • Clock distribution

    • Data Sheet, Rev. A, 5/08

    ADN4667
    3 V LVDS Quad CMOS Differential Line Driver
    ADN4667-fbl ADN4667-pc
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    Documentation

    Data Sheet 1

    Application Note 3

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    Tools & Simulations

    ADN4667 IBIS Model 1

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