ADN2917
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ADN2917

Continuous Rate 8.5 Gbps to 11.3 Gbps Clock and Data Recovery IC with Integrated Limiting Amp/EQ

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warning : NOT RECOMMENDED FOR NEW DESIGNS tooltip
warning : NOT RECOMMENDED FOR NEW DESIGNS tooltip
Part Details
Part Models 2
1ku List Price
price unavailable
Features
  • Serial data input: 8.5 Gbps to 11.3 Gbps
  • No reference clock required
  • Exceeds SONET/SDH requirements for jitter transfer/generation/tolerance
  • Quantizer sensitivity: 9.2 mV p-p typical (limiting amplifier mode)
  • Optional limiting amplifier and equalizer inputs
  • Programmable jitter transfer bandwidth to support G.8251 OTN
  • Programmable slice level
  • Sample phase adjust
  • Output polarity invert
  • Programmable LOS threshold via I2C
  • I2C to access optional features
  • LOS alarm (limiting amplifier mode only)
  • LOL indicator
  • PRBS generator/detector
  • Application-aware power
    • 352 mW at 8.5 Gbps, equalizer mode, no clock output
    • 430 mW at 11.3 Gbps, equalizer mode, no clock output
  • Power supplies: 1.2 V, flexible 1.8 V to 3.3 V, and 3.3 V
  • 4 mm × 4 mm 24-lead LFCSP
Additional Details
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The ADN2917 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 8.5 Gbps to 11.3 Gbps. The ADN2917 automatically locks to all data rates without the need for an external reference clock or programming. ADN2917 jitter performance exceeds all jitter specifications required by SONET/SDH, including jitter transfer, jitter generation, and jitter tolerance.

The ADN2917 provides manual or automatic slice adjust and manual sample phase adjusts. Additionally, the user can select a limiting amplifier or equalizer at the input. The equalizer is either adaptive or can be manually set.

The receiver front-end loss of signal (LOS) detector circuit indicates when the input signal level has fallen below a user-programmable threshold. The LOS detect circuit has hysteresis to prevent chatter at the LOS output. In addition, the input signal strength can be read through the I2C registers.

The ADN2917 also supports pseudorandom binary sequence (PRBS) generation, bit error detection, and input data rate readback features.

The ADN2917 is available in a compact 4 mm × 4 mm, 24-lead frame chip scale package (LFCSP). All ADN2917 specifications are defined over the ambient temperature range of −40°C to +85°C, unless otherwise noted.

Applications

  • SONET/SDH OC-192, 10GFC, and 10GE and all associated FECs
  • XFP, line cards, clocks, routers, repeaters, instruments
  • Any rate regenerators/repeaters
Part Models 2
1ku List Price
price unavailable

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Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
ADN2917ACPZ
  • HTML
  • HTML
ADN2917ACPZ-RL7
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  • HTML
Software & Part Ecosystem

Software & Part Ecosystem

Evaluation Kit

Evaluation Kits 1

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EVAL-ADN29XX

ADN2905/ADN2913/ADN2915/ADN2917 Evaluation Board

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EVAL-ADN29XX

ADN2905/ADN2913/ADN2915/ADN2917 Evaluation Board

ADN2905/ADN2913/ADN2915/ADN2917 Evaluation Board

Features and Benefits

  • Full featured evaluation board for the ADN2905/ADN2913/ADN2915/ADN2917
  • Configurable as PRBS generator or PRBS error detector
  • Locked to any rate, continuous mode, up to 11.3 Gbps input signal

Product Detail

The ADN2905, ADN2913, ADN2915, and ADN2917 provide the receiver functions of quantization, signal level detect, and clock/data recovery for a continuous signal data rate range from 6.5 Mbps to 11.3 Gbps. The ADN29xx automatically lock to such a data signal without referring to an external clock or extra programming. All SONET/SDH jitter requirements are exceeded, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for the –40°C to +85°C temperature range, unless otherwise noted.


For the best input signal detection, the ADN29xx input circuitry can be configured as a limiting amplifier, an equalizer, or a 0 dB equalizer. Additionally, the ADN29xx provide manual control of sampling phase and slice level adjust to optimize the incoming data eye detection.


The loss of signal (LOS) is available in limiting amplifier input mode only. The asserted LOS indicates that the input signal level has fallen below a preset threshold. The LOS detect circuit provides a typical 6.0 dB hysteresis to prevent LOS output chatter.


The asserted loss of lock (LOL) indicates when incoming signal rate shifts more than 1000 ppm away from the CDR VCO frequency.


The ADN29xx are available in a compact 4 mm × 4 mm, 24-lead chip scale package (LFCSP).


Full specifications on the ADN2905/ADN2913/ADN2915/ADN2917 are available in the product data sheet, which should be consulted in conjunction with this user guide when working with the evaluation board.


The ADN2905, ADN2913, ADN2915, and ADN2917 are pin-to-pin compatible devices and share the same evaluation board. Each EVALZ-ADN29xx evaluation board is populated by a different DUT: ADN2905 on the EVALZ-ADN2905, ADN2913 on the EVALZ-ADN2913, ADN2915 on the EVALZ-ADN2915, and ADN2917 on the EVALZ-ADN2917.

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